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@ycsin ycsin commented Nov 11, 2024

Note

First 4 commits came from #78496

Not polished yet, but the idea is there.

ycsin and others added 6 commits November 11, 2024 15:46
The `soc_per_core_init_hook()` function now has `void` type after
da118b9, so it should just return without any value.

Signed-off-by: Yong Cong Sin <[email protected]>
Signed-off-by: Yong Cong Sin <[email protected]>
Allow SoC to implement their custom per-core initialization function by
selecting `CONFIG_SOC_PER_CORE_INIT_HOOK` and implement
`soc_per_core_init_hook()`.

Signed-off-by: Maxim Adelman <[email protected]>
Signed-off-by: Yong Cong Sin <[email protected]>
Signed-off-by: Yong Cong Sin <[email protected]>
The function `pma_init_per_core()`, as its name suggest, should be
run from every core, so call it from `soc_per_core_init_hook()`

Signed-off-by: Yong Cong Sin <[email protected]>
Signed-off-by: Yong Cong Sin <[email protected]>
Refactor out the `soc_early_init_hook()` function from `pma.c` to
`soc.c` which is always compiled so that it can be extended to run
other init functions easily in the future. Then, restore the function
in `pma.c` to `pma_init()`.

Signed-off-by: Yong Cong Sin <[email protected]>
The currently IPI implementation assumes that CLINT exists in the
system, however, that might not be the case as IPI can be implemented
with certain PLIC as well, such as Andes NCEPLIC100 which supports
soft-triggering.

Refactor the CLINT-based IPI implementations into `ipi_clint.h`, and
create Kconfig that selects the CLINT implementation when
`sifive-clint0` exists and enabled, otherwise default to
`RISCV_SMP_IPI_CUSTOM` which allows a OOT implementation.

Signed-off-by: Yong Cong Sin <[email protected]>
Add PLIC-based IPI implementation.

Signed-off-by: Yong Cong Sin <[email protected]>
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npitre commented Nov 11, 2024

Does the PLIC support more than one IPI signal?

For example, on ARM64, the GIC provides several IRQ numbers that can be used
for IPIs. The scheduler IPI uses SGI#0, the domain synchronization uses
SGI#1, the FPU flush IPI uses SGI#2, etc.

The CLINT on RISC-V has only one IPI signal available. This is why there
is a software-based multiplexer on top. But if the PLIC or some other
implementation have more than one IPI signal then the multiplexer should
be moved to the CLINT abstraction and the other IPI implementations
do just like ARM64.

@ycsin
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ycsin commented Nov 12, 2024

Does the PLIC support more than one IPI signal?

I get what you mean now - Yes, for PLIC with soft triggering, we can dedicate one IRQ for each IPI signals and the software-based multiplexor can be eliminated

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2 participants