boards: added the Sensoan SGW-2 board

boards/sensoan/index.rst

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+.. _boards-sensoan:
+
+Sensoan
+#######
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*

boards/sensoan/sgw2/CMakeLists.txt

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+# Kconfig - SGW-2 board configuration
+#
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# Copyright (c) 2024 Sensoan Oy
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if((CONFIG_BOARD_SGW2_NRF9160 OR CONFIG_BOARD_SGW2_NRF9160_NS) AND CONFIG_BT_HCI)
+  zephyr_library()
+  zephyr_library_sources(nrf5340_reset.c)
+endif()

boards/sensoan/sgw2/Kconfig

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+# SGW-2 board configuration
+#
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# Copyright (c) 2024 Sensoan Oy
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_SGW2
+	# The GPIO driver is forced here to be enabled whenever nrf5340_reset.c
+	# is included. This is the case for sgw2/nrf9160 and sgw2/nrf9160/ns builds
+	# whenever BT_HCI is enabled.
+	select GPIO if (BOARD_SGW2_NRF9160 || BOARD_SGW2_NRF9160_NS) && BT_HCI
+
+if BOARD_SGW2_NRF5340_CPUAPP || BOARD_SGW2_NRF5340_CPUAPP_NS || BOARD_SGW2_NRF5340_CPUNET
+
+if BOARD_SGW2_NRF5340_CPUAPP || BOARD_SGW2_NRF5340_CPUAPP_NS
+
+config DOMAIN_CPUNET_BOARD
+	string
+	default "sgw2/nrf5340/cpunet"
+	help
+	  The board which will be used for CPUNET domain when creating a multi
+	  image application where one or more images should be located on
+	  another board. For example hci_rpmsg on the nRF5340_cpunet for
+	  Bluetooth applications.
+
+endif #  BOARD_SGW2_NRF5340_CPUAPP || BOARD_SGW2_NRF5340_CPUAPP_NS
+
+config DOMAIN_CPUAPP_BOARD
+	string
+	default "sgw2/nrf5340/cpuapp"
+	depends on BOARD_SGW2_NRF5340_CPUNET
+	help
+	  The board which will be used for CPUAPP domain when creating a multi
+	  image application where one or more images should be located on
+	  another board.
+
+endif # BOARD_SGW2_NRF5340_CPUAPP || BOARD_SGW2_NRF5340_CPUAPP_NS || BOARD_SGW2_NRF5340_CPUNET
+
+module=BOARD
+module-dep=LOG
+module-str=Log level for board
+source "${ZEPHYR_BASE}/subsys/logging/Kconfig.template.log_config"

boards/sensoan/sgw2/Kconfig.defconfig

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+# SGW2 board configuration
+#
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# Copyright (c) 2024 Sensoan Oy
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_SGW2_NRF9160 || BOARD_SGW2_NRF9160_NS
+
+# For the secure version of the board the firmware is linked at the beginning
+# of the flash, or into the code-partition defined in DT if it is intended to
+# be loaded by MCUboot. If the secure firmware is to be combined with a non-
+# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always
+# be restricted to the size of its code partition.
+# For the non-secure version of the board, the firmware
+# must be linked into the code-partition (non-secure) defined in DT, regardless.
+# Apply this configuration below by setting the Kconfig symbols used by
+# the linker according to the information extracted from DT partitions.
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
+
+config FLASH_LOAD_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+	depends on BOARD_SGW2_NRF9160 && TRUSTED_EXECUTION_SECURE
+
+if BOARD_SGW2_NRF9160_NS
+
+config FLASH_LOAD_OFFSET
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+config FLASH_LOAD_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+endif # BOARD_SGW2_NRF9160_NS
+
+config BT_HCI_VS
+	default y if BT
+
+config I2C
+	default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c)
+
+endif # BOARD_SGW2_NRF9160 || BOARD_SGW2_NRF9160_NS
+
+if  BOARD_SGW2_NRF5340_CPUAPP || BOARD_SGW2_NRF5340_CPUAPP_NS
+
+# Code Partition:
+#
+# For the secure version of the board the firmware is linked at the beginning
+# of the flash, or into the code-partition defined in DT if it is intended to
+# be loaded by MCUboot. If the secure firmware is to be combined with a non-
+# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always
+# be restricted to the size of its code partition.
+#
+# For the non-secure version of the board, the firmware
+# must be linked into the code-partition (non-secure) defined in DT, regardless.
+# Apply this configuration below by setting the Kconfig symbols used by
+# the linker according to the information extracted from DT partitions.
+
+# SRAM Partition:
+#
+# If the secure firmware is to be combined with a non-secure image
+# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always
+# be restricted to the secure image SRAM partition (sram-secure-partition).
+# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram
+# may be used by the image.
+#
+# For the non-secure version of the board, the firmware image SRAM is
+# always restricted to the allocated non-secure SRAM partition.
+#
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
+DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition
+
+if BOARD_SGW2_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE
+
+config FLASH_LOAD_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+config SRAM_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K)
+
+endif # BOARD_SGW2_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE
+
+if BOARD_SGW2_NRF5340_CPUAPP_NS
+
+config FLASH_LOAD_OFFSET
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+config FLASH_LOAD_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+endif # BOARD_SGW2_NRF5340_CPUAPP_NS
+
+config BT_HCI_IPC
+	default y if BT
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default 4096 if BT_HCI_IPC
+
+endif #  BOARD_SGW2_NRF5340_CPUAPP || BOARD_SGW2_NRF5340_CPUAPP_NS
+
+if BOARD_SGW2_NRF5340_CPUNET
+
+config BT_CTLR
+	default y if BT
+
+endif # BOARD_SGW2_NRF5340_CPUNET

boards/sensoan/sgw2/Kconfig.sgw2

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+# SGW-2 board configuration
+#
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# Copyright (c) 2024 Sensoan Oy
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_SGW2
+	select SOC_NRF9160_SICA if BOARD_SGW2_NRF9160 || BOARD_SGW2_NRF9160_NS
+	select SOC_NRF5340_CPUAPP_QKAA if BOARD_SGW2_NRF5340_CPUAPP
+	select SOC_NRF5340_CPUAPP_QKAA if BOARD_SGW2_NRF5340_CPUAPP_NS
+	select SOC_NRF5340_CPUNET_QKAA if BOARD_SGW2_NRF5340_CPUNET

boards/sensoan/sgw2/board.cmake

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+# Copyright (c) 2019 Nordic Semiconductor ASA.
+# Copyright (c) 2024 Sensoan Oy
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_BOARD_SGW2_NRF9160 OR CONFIG_BOARD_SGW2_NRF9160_NS)
+  if(CONFIG_BOARD_SGW2_NRF9160_NS)
+    set(TFM_PUBLIC_KEY_FORMAT "full")
+  endif()
+
+  if(CONFIG_TFM_FLASH_MERGED_BINARY)
+    set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
+  endif()
+  board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000")
+  include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
+  include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+  include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+elseif(CONFIG_BOARD_SGW2_NRF5340_CPUAPP OR CONFIG_BOARD_SGW2_NRF5340_CPUAPP_NS OR CONFIG_BOARD_SGW2_NRF5340_CPUNET)
+  if(CONFIG_BOARD_SGW2_NRF5340_CPUAPP_NS)
+    set(TFM_PUBLIC_KEY_FORMAT "full")
+  endif()
+
+  if(CONFIG_BOARD_SGW2_NRF5340_CPUAPP OR CONFIG_BOARD_SGW2_NRF5340_CPUAPP_NS)
+    board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000")
+  endif()
+
+  if(CONFIG_TFM_FLASH_MERGED_BINARY)
+    set_property(TARGET runners_yaml_props_target PROPERTY hex_file "${CMAKE_BINARY_DIR}/tfm_merged.hex")
+  endif()
+
+  if(CONFIG_BOARD_SGW2_NRF5340_CPUNET)
+    board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000")
+  endif()
+
+  include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
+  include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+endif()

boards/sensoan/sgw2/board.h

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+/*
+ * Copyright (c) 2024 Sensoan Oy
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/* Internal macros */
+#define PORT(_TYPE, _PIN)   _TYPE##_PORT_##_PIN
+#define PIN(_TYPE, _PIN)    _TYPE##_PIN_##_PIN
+#define GPIOAUX(_PORT)      &gpio##_PORT
+#define GPIO_BY_PORT(_PORT) GPIOAUX(_PORT)
+#define GPIO(_TYPE, _PIN)   GPIO_BY_PORT(PORT(_TYPE, _PIN))
+
+/**
+ * Rewrite a pin with a special type as the corresponding GPIO node and pin.
+ * These correspondences are encoded in the header files sgw2_nrf5340.h and
+ * sgw2_nrf9160.h contained in the board directory.
+ *
+ * @param _TYPE Pin type (allowed types are MCU_IF and EDGE_CONN)
+ * @param _PIN Pin number
+ */
+#define GPIO_AND_PIN(_TYPE, _PIN) GPIO(_TYPE, _PIN) PIN(_TYPE, _PIN)
+
+/**
+ * A wrapper for the NRF_PSEL macro that accepts pins with special types.
+ * These are translated into the corresponding GPIO ports and pins
+ * for the use of NRF_PSEL via the correspondences encoded in the header files
+ * sgw2_nrf5340.h and sgw2_nrf9160.h contained in the board directory.
+ *
+ * @param _FUN Pin function configuration passed to the NRF_PSEL macro
+ * @param _TYPE Pin type (allowed types are MCU_IF and EDGE_CONN)
+ * @param _PIN Pin number
+ */
+#define SGW_PSEL(_FUN, _TYPE, _PIN) NRF_PSEL(_FUN, PORT(_TYPE, _PIN), PIN(_TYPE, _PIN))
+
+#endif /* BOARD_H */

boards/sensoan/sgw2/board.yml

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+board:
+  name: sgw2
+  vendor: sensoan
+  socs:
+  - name: nrf9160
+    variants:
+    - name: 'ns'
+  - name: nrf5340
+    variants:
+    - name: 'ns'
+      cpucluster: 'cpuapp'