Add Support Artery Technology AT32F405(ARM Cortex M4F) SoC.

MAINTAINERS.yml

@@ -4986,6 +4986,17 @@ West:
   labels:
     - "platform: Ambiq"
 
+"West project: hal_at32":
+  status: maintained
+  maintainers:
+    - ubieda
+  collaborators:
+    - asmellby
+  files:
+    - modules/hal_at32/
+  labels:
+    - "platform: AT32"
+
 "West project: hal_atmel":
   status: maintained
   maintainers:

boards/artery/at_start_f405/Kconfig.at_start_f405

@@ -0,0 +1,5 @@
+# Copyright (c) 2018 Philémon Jaermann
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_AT_START_F405
+	select SOC_AT32F405

boards/artery/at_start_f405/at_start_f405-pinctrl.dtsi

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Maxjta
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/at32f405r(c-g-m)xx-pinctrl.h>
+
+&pinctrl {
+	usart1_default: usart1_default {
+		group1 {
+			pinmux = <USART1_TX_PA9>, <USART1_RX_PA10>;
+		};
+	};
+};

boards/artery/at_start_f405/at_start_f405.dts

@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2025 Maxjta
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <artery/at32f402_405/at32f405rct7.dtsi>
+#include "at_start_f405-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Artery AT-START-F405 board";
+	compatible = "artery,at_start_f405";
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		red_led: led2 {
+			gpios = <&gpiof 4 GPIO_ACTIVE_HIGH>;
+			label = "User LED2";
+		};
+
+		yellow_led: led3 {
+			gpios = <&gpiof 5 GPIO_ACTIVE_HIGH>;
+			label = "User LED3";
+		};
+
+		green_led: led4 {
+			gpios = <&gpiof 6 GPIO_ACTIVE_HIGH>;
+			label = "User LED4";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button: button {
+			label = "User";
+			gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &red_led;
+		led1 = &yellow_led;
+		led2 = &green_led;
+		sw0 = &user_button;
+	};
+};
+
+&gpioa {
+	status = "okay";
+};
+
+&gpiob {
+	status = "okay";
+};
+
+&gpioc {
+	status = "okay";
+};
+
+&gpiod {
+	status = "okay";
+};
+
+&gpiof {
+	status = "okay";
+};
+
+&clk_hick {
+	status = "okay";
+};
+
+&clk_hext {
+	clock-frequency = <12000000>;
+	status = "okay";
+};
+
+&sysclk {
+	clock-frequency = <DT_FREQ_M(216)>;
+	status = "okay";
+};
+
+&pll {
+	div-ms = <1>;
+	mul-ns = <72>;
+	div-fp = <2>;
+	div-fu = <5>;
+	clocks = <&clk_hext>;
+	status = "okay";
+};
+
+&crm {
+	clocks = <&pll>;
+	ahb-prescaler = <1>;
+	clock-frequency = <216000000>;
+	apb1-prescaler = <2>;
+	apb2-prescaler = <1>;
+	status = "okay";
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_default>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};

boards/artery/at_start_f405/at_start_f405.yaml

@@ -0,0 +1,13 @@
+identifier: at_start_f405
+name: Artery AT-START-F405
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+supported:
+  - gpio
+ram: 96
+flash: 256
+vendor: artery

boards/artery/at_start_f405/at_start_f405_defconfig

@@ -0,0 +1,19 @@
+# Copyright (c) 2025, Jun Tan <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable reset
+CONFIG_RESET=y

boards/artery/at_start_f405/board.cmake

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# keep first
+board_runner_args(pyocd "--target=at32f405rc")
+board_runner_args(jlink "--device=AT32F405RC" "--speed=4000")
+
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/artery/at_start_f405/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: at_start_f405
+  vendor: artery
+  socs:
+    - name: at32f405

boards/artery/at_start_f405/doc/index.rst

@@ -0,0 +1,91 @@
+.. zephyr:board:: at_start_f405
+
+Overview
+********
+
+The AT START F405 board features an ARM Cortex-M4 based AT32F405 MCU
+with a wide range of connectivity support and configurations.
+
+Hardware
+********
+
+- ARM Cortex-M4F Processor
+- Core clock up to 216 MHz
+- 256KB Flash memory
+- 96 KB SRAM
+- 1x12-bit 2MSPS ADC
+- Up to 6x USART and 2x UART
+- Up to 3x I2C
+- Up to 3x SPI
+- 1x QSPI interface
+- 1x CAN interface(2.0B Active)
+- 1x OTGHS on chip phy, Support usb2.0 high speed
+- 1x OTGFS Support usb2.0 Full speed
+- Up to 14 times
+- 2 x 7-channel DMA controllers
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Serial Port
+===========
+
+The AT-START-F405 board has one serial communication port. The default port
+is USART1 with TX connected at PA9 and RX at PA10.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Using ATLink or J-Link
+=======================
+The board comes with an embedded AT-Link programmer.
+You need to install CMSIS-Pack which is required by pyOCD
+when programming or debugging by the AT-Link programmer.
+Execute the following command to install CMSIS-Pack for AT32F405CCT7
+if not installed yet.
+
+   .. code-block:: console
+
+      pyocd pack install at32f405cct7
+
+Also, J-Link can be used to program the board via the SWD interface
+(PA13/SWDIO and PA14/SWCLK).
+
+#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/basic/blinky
+      :board: at_start_f405
+      :goals: build
+      :compact:
+
+#. To flash an image:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/basic/blinky
+      :board: at_start_f405
+      :goals: flash
+      :compact:
+
+   When using J-Link, append ``--runner jlink`` option after ``west flash``.
+
+   You should see blink LED2 on board AT-START-F405.
+
+#. To debug an image:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/basic/blinky
+      :board: at_start_f405
+      :goals: debug
+      :compact:
+
+   When using J-Link, append ``--runner jlink`` option after ``west debug``.
+
+References
+**********
+
+.. _microbit website: https://www.arterychip.com/en/product/AT32F405.jsp

boards/artery/index.rst

@@ -0,0 +1,10 @@
+.. _boards-artery:
+
+Artery Technology
+#################
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*

drivers/clock_control/CMakeLists.txt

@@ -5,6 +5,7 @@ zephyr_library()
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE              beetle_clock_control.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ADSP                clock_control_adsp.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ARM_SCMI            clock_control_arm_scmi.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AT32                clock_control_at32.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32               clock_control_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_FIXED_RATE_CLOCK    clock_control_fixed_rate.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_GD32                clock_control_gd32.c)

drivers/clock_control/Kconfig

@@ -76,6 +76,8 @@ source "drivers/clock_control/Kconfig.aspeed"
 
 source "drivers/clock_control/Kconfig.gd32"
 
+source "drivers/clock_control/Kconfig.at32"
+
 source "drivers/clock_control/Kconfig.sam"
 
 source "drivers/clock_control/Kconfig.si32"

drivers/clock_control/Kconfig.at32

@@ -0,0 +1,8 @@
+# Copyright (c) 2022 Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+config CLOCK_CONTROL_AT32
+	bool "AT32 clock control"
+	default y
+	depends on DT_HAS_ARTERY_AT32_CCTL_ENABLED
+	help
+	  Enable driver for AT32 Reset Clock Unit (CRM).