MSPI_DW DMA and Async support #94469

Hi-Im-David · 2025-08-13T16:03:44Z

PR for the mspi_dw driver to support Async and DMA transactions and support for the new nrf-mspi peripheral (name tbc). This peripheral is similar to the exmif in nRF54H20, using the same core designware IP, but has been configured to support DMA and slave mode. The DMA being used is part of the wrapper and not the core IP.

Concurrent Aync transactions and XiP support for nrf-mspi will be added in a future PR. The DMA support uses the DMA in a vendor specific wrapper.

Hi-Im-David · 2025-08-13T16:20:07Z

drivers/mspi/Kconfig.dw

anangl

I haven't managed to go through all the code yet but there is already quite a few issues to be addressed.

drivers/mspi/mspi_dw.h

drivers/mspi/mspi_dw_vendor_specific.h

drivers/mspi/mspi_dw.c

drivers/mspi/mspi_dw_vendor_specific.h

drivers/mspi/mspi_dw.c

dts/bindings/mspi/snps,designware-ssi.yaml

drivers/mspi/mspi_dw.c

Hi-Im-David · 2025-09-24T17:04:23Z

I haven't managed to go through all the code yet but there is already quite a few issues to be addressed.

Thanks very much for your review @anangl, lots of helpful comments. Hopefully the latest push fixes most of them. I've also added a few replies to your comments for your input.

drivers/mspi/mspi_dw.c

anangl · 2025-10-01T15:09:23Z

drivers/mspi/mspi_dw_vendor_specific.h

+/* Number of jobs needed for transmit trasaction */
+#define MAX_NUM_JOBS 4
+/* Just support 1 trasaction for each peripheral as concurrent transactions aren't supported yet*/
+#define MAX_CONCURR_TRANSACTIONS 1


I'm not sure I understand what you actually mean by concurrent transactions and how those could be supported by the driver.

By this, I mean multiple requests of mspi_transceive() that get buffered by the driver. Not sure if this was going to be needed but currently if another request is made while a transaction is already in progress it will just reject the request and say "Async transfer already in progress".

The requests would need to be somehow queued then. I think it's better to drop this for now.

drivers/mspi/mspi_dw_vendor_specific.h

anangl · 2025-10-01T15:22:49Z

drivers/mspi/mspi_dw_vendor_specific.h

+	preg->CONFIG.TXBURSTLENGTH = (config->tx_fifo_depth_minus_1+1)-config->dma_tx_data_level;
+	preg->CONFIG.RXBURSTLENGTH = config->dma_rx_data_level+1;
+	preg->DMA.CONFIG.LISTPTR = (uint32_t)transfer_list;
+	preg->INTEN = BIT(QSPI_INTEN_DMADONE_Pos);


This clears BIT(QSPI_INTENSET_CORE_Pos), why?

setting QSPI_INTENSET_CORE_Pos here seems to brick the system, not sure why but left a comment to address in future as I'm assuming this is needed for XiP? The system will still work in FIFO mode since this DMA function will never be called.

setting QSPI_INTENSET_CORE_Pos here seems to brick the system, not sure why but left a comment to address in future as I'm assuming this is needed for XiP?

XIP has nothing to do with interrupts. Something is apparently wrong and it would be good clarify this.

The system will still work in FIFO mode since this DMA function will never be called.

Not really. Once you perform a DMA transfer, you won't be able to perform a PIO one anymore, as the related interrupt will be disabled.

drivers/mspi/mspi_dw.c

Support for new MSPI peripheral where there is no PSEL so pins are setup through CTRLSEL. Signed-off-by: David Jewsbury <[email protected]>

This is a new callback option that drivers can use for when a request or xfer has timed out. E.g if an Async RX request never received anything, this callback can be used so a user can clean up their application. Signed-off-by: David Jewsbury <[email protected]>

enum mspi_op_mode in mspi.h has different syntax to this binding. Aligning these will allow for cleaner code in the implmented drivers. Signed-off-by: David Jewsbury <[email protected]>

Handling of asynchronous transfers uses the system workqueue, hence they are not available when multithreading is disabled. Also add missing dependency on multithreading in the MSPI_DW_HANDLE_FIFOS_IN_SYSTEM_WORKQUEUE Kconfig option. Signed-off-by: David Jewsbury <[email protected]> Signed-off-by: Andrzej Głąbek <[email protected]>

MSPI slave mode is selected through devicetree using the op-mode property. Mode selected by SSIISMST bit in the CTRLR0 register. EXMIF can only be Master (controller). Signed-off-by: David Jewsbury <[email protected]>

Initial DMA support. DMA supports implementation of SSI IP but using vendor specific DMA in the wrapper. The setup of the DMA is done in mspi_dw_vendor_specific.h. Signed-off-by: David Jewsbury <[email protected]>

The nrf-mspi peripheral is similar to EXMIF on nrf54h20 but supports DMA and slave-mode. The wrapper around the SSI IP is also different with DMA features. Signed-off-by: David Jewsbury <[email protected]>

sonarqubecloud · 2025-10-14T11:23:57Z

Quality Gate passed

Issues
4 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

anangl · 2025-10-08T07:13:11Z

drivers/mspi/mspi_dw_vendor_specific.h

+	preg->CONFIG.TXBURSTLENGTH = (config->tx_fifo_depth_minus_1+1)-config->dma_tx_data_level;
+	preg->CONFIG.RXBURSTLENGTH = config->dma_rx_data_level+1;
+	preg->DMA.CONFIG.LISTPTR = (uint32_t)transfer_list;
+	preg->INTEN = BIT(QSPI_INTEN_DMADONE_Pos);


setting QSPI_INTENSET_CORE_Pos here seems to brick the system, not sure why but left a comment to address in future as I'm assuming this is needed for XiP?

XIP has nothing to do with interrupts. Something is apparently wrong and it would be good clarify this.

The system will still work in FIFO mode since this DMA function will never be called.

Not really. Once you perform a DMA transfer, you won't be able to perform a PIO one anymore, as the related interrupt will be disabled.

anangl · 2025-10-14T11:45:49Z

dts/bindings/mspi/snps,designware-ssi.yaml

+      When in DMA mode, the transmit data level field controls the level at which a DMA request
+      is made by the transmit logic. A request to transmit is generated when the number of
+      valid data entries in the transmit FIFO is equal to or below this field value. Lower values
+      mean less frequent DMA triggers with larger bursts. Higher values mean fewer, larger bursts


Suggested change

mean less frequent DMA triggers with larger bursts. Higher values mean fewer, larger bursts

mean less frequent DMA triggers with larger bursts. Higher values mean fewer, smaller bursts

anangl · 2025-10-14T11:52:37Z

dts/bindings/mspi/snps,designware-ssi.yaml

+    description: |
+      When in DMA mode, the receive data level field controls the level at which a DMA request
+      is made by the receive logic. A request to receive is generated when the number of
+      valid data entries in the receive FIFO is greater than this value + 1. Lower values mean


This field description in the SSI Databook says "equal to or above this field value + 1", so:

Suggested change

valid data entries in the receive FIFO is greater than this value + 1. Lower values mean

valid data entries in the receive FIFO is greater than this value. Lower values mean

anangl · 2025-10-14T11:54:14Z

dts/bindings/mspi/snps,designware-ssi.yaml

+      When in DMA mode, the receive data level field controls the level at which a DMA request
+      is made by the receive logic. A request to receive is generated when the number of
+      valid data entries in the receive FIFO is greater than this value + 1. Lower values mean
+      more frequent DMA triggers and higher values mean larger less frequent bursts. Range: 1-15


I believe the range should be 0-15, for both these properties.

anangl · 2025-10-14T11:55:29Z

drivers/mspi/mspi_dw.h

+#define DMACR_RDMAE_BIT			BIT(0)
+
+/* DMATDLR - DMA Transmit Data Level */
+#define DMA_TDLR_DMATDL_MASK		 GENMASK(3, 0)


Suggested change

#define DMA_TDLR_DMATDL_MASK GENMASK(3, 0)

#define DMATDLR_DMATDL_MASK GENMASK(3, 0)

anangl · 2025-10-14T14:42:26Z

drivers/mspi/mspi_dw.c

+	void *dma_transfer_list;
+	void *dma_joblist;


Why not introduce instead a generic vendor_specific_data pointer (together with VENDOR_SPECIFIC_DATA_DEFINE() and VENDOR_SPECIFIC_DATA_GET() macros) that would be available always, not only when DMA is used? This would be more flexible.

anangl · 2025-10-14T14:46:27Z

drivers/mspi/mspi_dw_vendor_specific.h

+	if (!transfer_list) {
+		LOG_ERR("DMA transfer list not available");
+		return -ENODEV;
+	}


Why would this list be not available? It is now allocated statically.

anangl · 2025-10-14T14:49:21Z

drivers/mspi/mspi_dw_vendor_specific.h

+#define MSPI_DW_DMA_XFER_LIST_GET(inst) &mspi_dw_##inst##_transfer_list
+#define MSPI_DW_DMA_JOBLIST_GET(inst) &mspi_dw_##inst##_joblist
+
+static inline void vendor_specific_start_dma_xfer(const struct device *dev)


Is it actually beneficial to have three separate functions: vendor_specific_start_dma_xfer(), vendor_specific_setup_dma_xfer(), and vendor_specific_dma_accessible_check(), instead of just one that would do all that is needed to start the DMA transfer?

anangl · 2025-10-14T14:54:55Z

drivers/mspi/mspi_dw.c

-				1 * RX_FIFO_DEPTH(inst) / 8 - 1)
-
+				1 * RX_FIFO_DEPTH(inst) / 8 - 1)	\
+	IF_ENABLED(CONFIG_MSPI_DMA, (,				\


This looks quite weird. I think it would be better to use a separate macro for DMA data levels that would be called from IF_ENABLED(CONFIG_MSPI_DMA, ).

anangl · 2025-10-14T14:56:44Z

drivers/mspi/mspi_dw.c

+		}
+#if defined(CONFIG_MSPI_DMA)
+		else if (dev_data->xfer.xfer_mode == MSPI_DMA) {
+			imr = IMR_RXFIM_BIT;


Is this actually needed? The SSI interrupts don't seem to be used for DMA transfers.

Hi-Im-David marked this pull request as draft August 13, 2025 16:05

zephyrbot added area: MSPI platform: nRF Nordic nRFx area: Pinctrl labels Aug 13, 2025

zephyrbot requested review from anangl, gmarull, jaz1-nordic, kl-cruz, magp-nordic, masz-nordic, nika-nordic and swift-tk August 13, 2025 16:10

zephyrbot assigned swift-tk Aug 13, 2025

Hi-Im-David changed the title ~~[WIP] Mspi dw dma async support~~ [WIP] MSPI_DW DMA and Async support Aug 13, 2025

Hi-Im-David changed the title ~~[WIP] MSPI_DW DMA and Async support~~ MSPI_DW DMA and Async support Aug 13, 2025

carlescufi assigned anangl Aug 14, 2025

Hi-Im-David force-pushed the mspi-dw-dma-async-support branch 2 times, most recently from ce8a013 to c095bba Compare August 15, 2025 16:14

swift-tk reviewed Aug 16, 2025

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drivers/mspi/Kconfig.dw Outdated Show resolved Hide resolved

Hi-Im-David force-pushed the mspi-dw-dma-async-support branch 4 times, most recently from 266a237 to aa46e61 Compare August 20, 2025 14:48

Hi-Im-David marked this pull request as ready for review August 20, 2025 14:53

Hi-Im-David force-pushed the mspi-dw-dma-async-support branch 3 times, most recently from 3b17e2e to 3c55ba4 Compare August 27, 2025 10:26

zephyrbot added the area: Devicetree label Aug 27, 2025

zephyrbot requested a review from decsny August 27, 2025 10:27

swift-tk previously approved these changes Sep 17, 2025

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anangl requested changes Sep 18, 2025

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anangl reviewed Sep 22, 2025

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Hi-Im-David dismissed swift-tk’s stale review via 2827f5e September 24, 2025 16:28

Hi-Im-David force-pushed the mspi-dw-dma-async-support branch from 8761bd1 to 2827f5e Compare September 24, 2025 16:28

zephyrbot requested review from bjarki-andreasen and lstnl September 24, 2025 16:29

Hi-Im-David force-pushed the mspi-dw-dma-async-support branch from 2827f5e to 235a0c3 Compare September 24, 2025 17:00

Hi-Im-David requested a review from anangl September 24, 2025 17:02

Hi-Im-David force-pushed the mspi-dw-dma-async-support branch 2 times, most recently from 0fa1414 to 1d94cb0 Compare September 26, 2025 15:09

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Hi-Im-David force-pushed the mspi-dw-dma-async-support branch from 1d94cb0 to af0dc30 Compare October 3, 2025 11:08

zephyrbot added area: Devicetree Bindings area: Boards/SoCs labels Oct 3, 2025

Hi-Im-David force-pushed the mspi-dw-dma-async-support branch from af0dc30 to ebd36d4 Compare October 3, 2025 11:22

Hi-Im-David requested a review from anangl October 3, 2025 11:27

Hi-Im-David added 3 commits October 13, 2025 11:09

drivers: pinctrl: nrf: add support for MSPI

3779d76

Support for new MSPI peripheral where there is no PSEL so pins are setup through CTRLSEL. Signed-off-by: David Jewsbury <[email protected]>

dts: mspi: Align op-mode binding with mspi.h enum

cb25ddc

enum mspi_op_mode in mspi.h has different syntax to this binding. Aligning these will allow for cleaner code in the implmented drivers. Signed-off-by: David Jewsbury <[email protected]>

Hi-Im-David force-pushed the mspi-dw-dma-async-support branch from ebd36d4 to 694e6ab Compare October 14, 2025 10:25

Hi-Im-David requested a review from swift-tk October 14, 2025 10:27

anangl and others added 4 commits October 14, 2025 11:47

drivers: mspi_dw: Add support for slave mode

1006411

MSPI slave mode is selected through devicetree using the op-mode property. Mode selected by SSIISMST bit in the CTRLR0 register. EXMIF can only be Master (controller). Signed-off-by: David Jewsbury <[email protected]>

drivers: mspi: mspi_dw: Add DMA support

50bf045

Initial DMA support. DMA supports implementation of SSI IP but using vendor specific DMA in the wrapper. The setup of the DMA is done in mspi_dw_vendor_specific.h. Signed-off-by: David Jewsbury <[email protected]>

drivers: mspi: mspi_dw: Add support for nrf-mspi peripheral

523f677

The nrf-mspi peripheral is similar to EXMIF on nrf54h20 but supports DMA and slave-mode. The wrapper around the SSI IP is also different with DMA features. Signed-off-by: David Jewsbury <[email protected]>

Hi-Im-David force-pushed the mspi-dw-dma-async-support branch from 694e6ab to 523f677 Compare October 14, 2025 10:51

anangl reviewed Oct 14, 2025

View reviewed changes

	mean less frequent DMA triggers with larger bursts. Higher values mean fewer, larger bursts
	mean less frequent DMA triggers with larger bursts. Higher values mean fewer, smaller bursts

	valid data entries in the receive FIFO is greater than this value + 1. Lower values mean
	valid data entries in the receive FIFO is greater than this value. Lower values mean

	#define DMA_TDLR_DMATDL_MASK GENMASK(3, 0)
	#define DMATDLR_DMATDL_MASK GENMASK(3, 0)

MSPI_DW DMA and Async support #94469

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MSPI_DW DMA and Async support #94469

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