Add support for the N308 rcpu in the SpacemiT K1 SoC and BananaPi BPI-F3 board

boards/bananapi/bpi_f3/Kconfig.bpi_f3

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Junhui Liu <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_BPI_F3
+	select SOC_K1_N308

boards/bananapi/bpi_f3/board.cmake

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd.cfg")
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/bananapi/bpi_f3/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: bpi_f3
+  full_name: BPI-F3
+  vendor: bananapi
+  socs:
+    - name: k1

boards/bananapi/bpi_f3/bpi_f3_k1_n308.dts

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Junhui Liu <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <spacemit/k1_n308.dtsi>
+
+/ {
+	model = "Banana Pi BPI-F3";
+	compatible = "bananapi,bpi-f3";
+
+	chosen {
+		zephyr,sram = &sram;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+};

boards/bananapi/bpi_f3/bpi_f3_k1_n308.yaml

@@ -0,0 +1,9 @@
+identifier: bpi_f3/k1/n308
+name: Banana Pi BPI-F3
+type: mcu
+arch: riscv
+ram: 256
+toolchain:
+  - zephyr
+supported:
+  - uart

boards/bananapi/bpi_f3/bpi_f3_k1_n308_defconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2025 Junhui Liu <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+# enable uart driver
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# uart console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

boards/bananapi/bpi_f3/doc/index.rst

@@ -0,0 +1,110 @@
+.. zephyr:board:: bpi_f3
+
+Overview
+********
+
+The `Banana Pi`_ BPI-F3 is an industrial-grade RISC-V development board. It is
+designed with the SpacemiT K1 SoC, featuring eight X60 cores and a single N308
+core. Currently, Zephyr OS supports the N308 core.
+
+Hardware
+********
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+Check the `schematic`_ for more details.
+
++--------+-------------+---------------------+
+| Name   | Function    | Usage               |
++========+=============+=====================+
+| GPIO47 | R_UART0_TXD | UART Console        |
++--------+-------------+---------------------+
+| GPIO48 | R_UART0_RXD | UART Console        |
++--------+-------------+---------------------+
+| GPIO70 | PRI_TDI     | JTAG Interface      |
++--------+-------------+---------------------+
+| GPIO71 | PRI_TMS     | JTAG Interface      |
++--------+-------------+---------------------+
+| GPIO72 | PRI_TCK     | JTAG Interface      |
++--------+-------------+---------------------+
+| GPIO73 | PRI_TDO     | JTAG Interface      |
++--------+-------------+---------------------+
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Flashing
+========
+
+Here is an example for building and flashing the :zephyr:code-sample:`hello_world`
+application for the board:
+
+Currently, you need to boot the `Bianbu`_ image provided by the vendor. This
+will enable the N308 core and configure uart0 for the N308. Afterward, you can
+load the Zephyr application using JTAG.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: bpi_f3/k1/n308
+   :goals: flash
+
+After flashing, you should see message similar to the following in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v4.2.0-2578-g6e6daeb40b24 ***
+   Hello World! bpi_f3/k1/n308
+
+You can flash the board using an external debug adapter, such as CMSIS-DAP
+by default. Specify the interface using the ``OPENOCD_INTERFACE`` environment
+variable before running ``west flash``.
+
+For example:
+
+.. code-block:: console
+
+   $ export OPENOCD_INTERFACE=cmsis-dap
+   $ west flash
+
+   $ export OPENOCD_INTERFACE=jlink
+   $ west flash
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: bpi_f3/k1/n308
+   :goals: debug
+
+Step through the application in your debugger, and you should see a message
+similar to the following in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v4.2.0-2578-g6e6daeb40b24 ***
+   Hello World! bpi_f3/k1/n308
+
+References
+**********
+
+.. target-notes::
+
+.. _Banana Pi:
+   https://banana-pi.org/
+
+.. _schematic:
+    https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3/
+
+.. _Bianbu:
+   https://bianbu.spacemit.com/

boards/bananapi/bpi_f3/support/openocd.cfg

@@ -0,0 +1,41 @@
+if {[info exists env(OPENOCD_INTERFACE)]} {
+	set INTERFACE $env(OPENOCD_INTERFACE)
+} else {
+	set INTERFACE "cmsis-dap"
+}
+
+source [find interface/$INTERFACE.cfg]
+
+transport select jtag
+
+adapter speed 2000
+
+set _TARGET rcpu
+set _CHIPNAME k1
+
+jtag newtap pre unknown -irlen 1 -expected-id 0x00000000 -disable
+jtag configure pre.unknown -event tap-enable ""
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10308A6D -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable ""
+
+jtag newtap post unknown -irlen 9 -expected-id 0x08501C0D -ignore-version
+
+jtag configure post.unknown -event setup {
+    global _CHIPNAME 0xe
+
+    irscan post.unknown 0x98
+    drscan post.unknown 16 0xe
+
+    jtag tapenable pre.unknown
+    jtag tapenable $_CHIPNAME.cpu
+}
+
+set _TARGETNAME $_CHIPNAME.cpu_$_TARGET
+
+target create $_TARGETNAME.0 riscv -chain-position $_CHIPNAME.cpu
+
+$_TARGETNAME.0 configure -event examine-start {
+    adapter speed 8000
+    puts [ adapter speed ]
+}

boards/bananapi/index.rst

@@ -0,0 +1,10 @@
+.. _boards-bananapi:
+
+BananaPi
+########
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*

drivers/serial/uart_ns16550.c

@@ -115,6 +115,7 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
 #define IER_TBE 0x02   /* transmit bit enable */
 #define IER_LSR 0x04   /* line status interrupts */
 #define IER_MSI 0x08   /* modem status interrupts */
+#define IER_UUE 0x40   /* UART Unit Enable (XScale) */
 
 /* equates for interrupt identification register */
 
@@ -732,7 +733,11 @@ static int uart_ns16550_configure(const struct device *dev,
 	(void)ns16550_read_char(dev, &c);
 
 	/* disable interrupts  */
+#if DT_HAS_COMPAT_STATUS_OKAY(intel_xscale_uart)
+	ns16550_outbyte(dev_cfg, IER(dev), IER_UUE);
+#else
 	ns16550_outbyte(dev_cfg, IER(dev), 0x00);
+#endif
 	ret = 0;
 
 out:

dts/bindings/cpu/nuclei,n308.yaml

@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Junhui Liu <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuclei N308 RISC-V Core
+
+compatible: "nuclei,n308"
+
+include: riscv,cpus.yaml

dts/bindings/serial/intel,xscale-uart.yaml

@@ -0,0 +1,5 @@
+description: Intel XScale PXA UART
+
+compatible: "intel,xscale-uart"
+
+include: ns16550.yaml

dts/bindings/vendor-prefixes.txt

@@ -1,4 +1,4 @@
 # Device tree binding vendor prefix registry. Keep this list in
 # alphabetical order.
 #
 # This isn't an exhaustive list, but you should add new prefixes to it
@@ -654,6 +654,7 @@
 solidrun	SolidRun
 solomon	Solomon Systech Limited
 sony	Sony Corporation
+spacemit	SpacemiT Technology Co. Ltd
 spansion	Spansion Inc.
 sparkfun	SparkFun Electronics
 sprd	Spreadtrum Communications Inc.

dts/riscv/spacemit/k1_n308.dtsi

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2025 Junhui Liu <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+#include <mem.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu: cpu@0 {
+			clock-frequency = <0x20000>;
+			compatible = "nuclei,n308", "riscv";
+			riscv,isa = "rv32imafdc_zicsr_zifencei";
+			reg = <0>;
+		};
+	};
+
+	sram: memory@0 {
+		compatible = "mmio-sram";
+		reg = <0x00000000 DT_SIZE_K(256)>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&eclic>;
+		ranges;
+
+		eclic: interrupt-controller@e0020000 {
+			compatible = "nuclei,eclic";
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg =  <0xe0020000 0x2000>;
+		};
+
+		systimer: timer@e0030000 {
+			compatible = "nuclei,systimer", "riscv,machine-timer";
+			reg = <0xe0030000 0x8 0xe0030008 0x8>;
+			reg-names = "mtime", "mtimecmp";
+			interrupts-extended = <&eclic 7 0>;
+		};
+
+		uart0: uart@c0881000 {
+			compatible = "intel,xscale-uart", "ns16550";
+			reg = <0xc0881000 0x1000>;
+			interrupts = <63 0>;
+			reg-shift = <2>;
+			clock-frequency = <DT_FREQ_M(26)>;
+			status = "disabled";
+		};
+
+		uart1: uart@c088d000 {
+			compatible = "intel,xscale-uart", "ns16550";
+			reg = <0xc088d000 0x1000>;
+			interrupts = <36 0>;
+			reg-shift = <2>;
+			clock-frequency = <DT_FREQ_M(26)>;
+			status = "disabled";
+		};
+	};
+};

soc/spacemit/k1/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/spacemit/k1/Kconfig

@@ -0,0 +1,17 @@
+# Copyright (c) 2025 Junhui Liu <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_K1_N308
+	select RISCV
+	select RISCV_PRIVILEGED
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_F
+	select RISCV_ISA_EXT_D
+	select RISCV_ISA_EXT_C
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+	select RISCV_HAS_CLIC
+	select INCLUDE_RESET_VECTOR
+	select ATOMIC_OPERATIONS_C

soc/spacemit/k1/Kconfig.defconfig

@@ -0,0 +1,28 @@
+# Copyright (c) 2025 Junhui Liu <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_KEY_STONE
+
+if SOC_K1_N308
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config RISCV_HART_MASK
+	default 0
+
+config RV_BOOT_HART
+	default 1
+
+config RISCV_MCAUSE_EXCEPTION_MASK
+	default 0xFFF
+
+config NUM_IRQS
+	default 80
+
+config RISCV_SOC_INTERRUPT_INIT
+	default y
+
+endif # SOC_K1_N308
+
+endif # SOC_SERIES_KEY_STONE