soc: arm: add FocalTech FT9001 SoC and evaluation board support

boards/focaltech/ft9001_eval/Kconfig.ft9001_eval

@@ -0,0 +1,5 @@
+# Copyright (c) 2025, FocalTech Systems CO.,Ltd
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FT9001_EVAL
+	select SOC_FT9001

boards/focaltech/ft9001_eval/board.cmake

@@ -0,0 +1,7 @@
+# Copyright (c) 2025, FocalTech Systems CO.,Ltd
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=FT9001" "--speed=4000")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/focaltech/ft9001_eval/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: ft9001_eval
+  full_name: FocalTech FT9001 Evaluation Board
+  vendor: focaltech
+  socs:
+    - name: ft9001

boards/focaltech/ft9001_eval/doc/index.rst

@@ -0,0 +1,44 @@
+:orphan:
+
+.. _focaltech_ft9001_eval:
+
+.. zephyr:board:: ft9001_eval
+
+FT9001 Evaluation Board
+#######################
+
+The **FT9001-EVAL** board is a hardware platform designed for evaluating and
+debugging the FocalTech FT9001 MCU, a high-performance ARM Cortex-M4F processor
+running at up to 160 MHz.
+
+It includes 32 KB of ROM and 256 KB of RAM, divided into 224 KB of standard SRAM
+and a distinct 32 KB DBUS-connected block.
+
+Hardware
+********
+
+- FocalTech FT9001 SoC (ARM Cortex-M4F compatible)
+- 32 KB boot ROM
+- 256 KB on-chip SRAM:
+  - 224 KB standard SRAM
+  - 32 KB DBUS-connected SRAM
+- 2 MB external flash memory (SPI interface)
+- 2x UART interfaces
+- 2x SPI interface
+- External GPIO pins with interrupt capability
+
+Supported Features
+******************
+
+.. zephyr:board-supported-hw::
+
+Building and Running
+********************
+
+Build and flash the :zephyr:code-sample:`hello_world` sample application:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: ft9001_eval
+   :goals: build flash
+   :compact:

boards/focaltech/ft9001_eval/ft9001_eval-pinctrl.dtsi

@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2025, FocalTech Systems CO.,Ltd
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/focaltech_ft9001_pinctrl.h>
+
+&pinctrl {
+	usart3_default: usart3_default {
+		group1 {
+			pinmux = <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SCICR_OFFSET, 25, 1)>,
+					 <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SCICR_OFFSET, 26, 1)>;
+		};
+
+		group2 {
+			/* Disable I2S */
+			pinmux = <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SWAPCR3_OFFSET, 9, 0)>,
+					 <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SWAPCR3_OFFSET, 12, 0)>;
+		};
+
+		group3 {
+			/* Disable PWMT1 */
+			pinmux = <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SWAPCR4_OFFSET, 24, 0)>,
+					 <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SWAPCR4_OFFSET, 29, 0)>;
+		};
+	};
+
+	/* Pin28 configured as GINT40 */
+	gint40_default: gint40_default {
+		group1 {
+			/* First level mux: SSI5 -> SPI1_SS */
+			pinmux = <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SWAPCR5_OFFSET, 15, 0)>;
+		};
+
+		group2 {
+			/* Second level mux: SPI1_SS -> GINT40 */
+			pinmux = <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SWAPCR2_OFFSET, 8, 1)>;
+		};
+	};
+
+	/* Pin26 configured as GINT41 */
+	gint41_default: gint41_default {
+		group1 {
+			/* First level mux: SSI5 -> SPI1_SCK */
+			pinmux = <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SWAPCR5_OFFSET, 14, 0)>;
+		};
+
+		group2 {
+			/* Second level mux: SPI1_SCK -> GINT41 */
+			pinmux = <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SWAPCR2_OFFSET, 9, 1)>;
+		};
+	};
+
+	/* Pin29 configured as GINT42 */
+	gint42_default: gint42_default {
+		group1 {
+			/* First level mux: SSI5 -> SPI1_MISO */
+			pinmux = <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SWAPCR5_OFFSET, 13, 0)>;
+		};
+
+		group2 {
+			/* Second level mux: SPI1_MISO -> GINT42 */
+			pinmux = <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SWAPCR2_OFFSET, 10, 1)>;
+		};
+	};
+
+	/* Pin27 configured as GINT43 */
+	gint43_default: gint43_default {
+		group1 {
+			/* First level mux: SSI5 -> SPI1_MOSI */
+			pinmux = <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SWAPCR5_OFFSET, 12, 0)>;
+		};
+
+		group2 {
+			/* Second level mux: SPI1_MOSI -> GINT43 */
+			pinmux = <FOCALTECH_PINMUX(FOCALTECH_IOCTRL_SWAPCR2_OFFSET, 11, 1)>;
+		};
+	};
+};

boards/focaltech/ft9001_eval/ft9001_eval.dts

@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2025, FocalTech Systems CO.,Ltd
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <focaltech/ft9001/ft9001.dtsi>
+#include "ft9001_eval-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "FocalTech FT9001 Evaluation Board";
+	compatible = "focaltech,ft9001-eval", "focaltech,ft9001";
+
+	chosen {
+		zephyr,console = &usart2;
+		zephyr,shell-uart = &usart2;
+		zephyr,flash = &flash0;
+		zephyr,sram = &sram0;
+		zephyr,sram2 = &sramd0;
+		zephyr,flash-controller = &efm;
+		zephyr,code-partition = &app_partition;
+	};
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		romcfg_partition: partition@0 {
+			label = "romcfg";
+			reg = <0x00000000 0x00001000>;
+			read-only;
+		};
+
+		app_partition: partition@1000 {
+			label = "app";
+			reg = <0x00001000 0x001FF000>;
+		};
+	};
+};
+
+&usart2 {
+	current-speed = <115200>;
+	parity = "none";
+	stop-bits = "1";
+	data-bits = <8>;
+	hw-flow-control;
+	status = "okay";
+};
+
+&efm {
+	status = "okay";
+};
+
+&eport1 {
+	mask = <0x20>;
+	ngpios = <8>;
+	status = "okay";
+};
+
+&eport5 {
+	mask = <0xFF>;
+	ngpios = <8>;
+	status = "okay";
+};
+
+&eport7 {
+	mask = <0x3C>;
+	ngpios = <8>;
+	status = "okay";
+};

boards/focaltech/ft9001_eval/ft9001_eval.yaml

@@ -0,0 +1,12 @@
+identifier: ft9001_eval
+name: FocalTech FT9001 Evaluation Board
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 256
+flash: 2048
+supported:
+  - serial
+vendor: focaltech

boards/focaltech/ft9001_eval/ft9001_eval_defconfig

@@ -0,0 +1,10 @@
+# Copyright (c) 2025, FocalTech Systems CO.,Ltd
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_USE_DT_CODE_PARTITION=y

boards/focaltech/ft9001_eval/support/openocd.cfg

@@ -0,0 +1,31 @@
+# Copyright (c) 2025, FocalTech Systems CO.,Ltd
+# SPDX-License-Identifier: Apache-2.0
+
+# FT9001 OpenOCD Configuration
+#
+# This configuration supports debugging the FT9001 evaluation board
+# using CMSIS-DAP compatible debuggers (such as DAPLink, J-Link, etc.)
+#
+# Usage: openocd -f boards/arm/ft9001_eval/support/openocd.cfg
+
+source [find interface/cmsis-dap.cfg]
+transport select swd
+
+set CHIPNAME ft9001
+set CPUTAPID 0x790007a3
+
+source [find target/stm32f4x.cfg]
+
+reset_config trst_and_srst separate
+
+# Configure target events for better debugging experience
+$_TARGETNAME configure -event gdb-attach {
+	echo "Debugger attaching: halting execution"
+	reset halt
+	gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+	echo "Debugger detaching: resuming execution"
+	resume
+}

drivers/clock_control/CMakeLists.txt

@@ -133,3 +133,4 @@ endif()
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AST10X0 clock_control_ast10x0.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MAX32 clock_control_max32.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_WCH_RCC clock_control_wch_rcc.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_FOCALTECH_FT9001 clock_control_ft9001.c)

drivers/clock_control/Kconfig

@@ -34,6 +34,8 @@ source "drivers/clock_control/Kconfig.beetle"
 
 source "drivers/clock_control/Kconfig.bflb"
 
+source "drivers/clock_control/Kconfig.focaltech"
+
 source "drivers/clock_control/Kconfig.fixed"
 
 source "drivers/clock_control/Kconfig.lpc11u6x"

drivers/clock_control/Kconfig.focaltech

@@ -0,0 +1,14 @@
+# Copyright (c) 2025, FocalTech Systems CO.,Ltd
+# SPDX-License-Identifier: Apache-2.0
+
+config CLOCK_CONTROL_FOCALTECH_FT9001
+	bool "FocalTech FT9001 Clock Power Module (CPM) driver"
+	default y
+	depends on DT_HAS_FOCALTECH_FT9001_CPM_ENABLED
+	help
+	  Enable clock control driver for FocalTech FT9001 SoC.
+	  This driver provides support for controlling peripheral
+	  clocks through the Clock Power Module (CPM) which manages
+	  clock gating for various on-chip peripherals including
+	  UART, SPI, I2C, CAN, USB, crypto engines, and memory
+	  controllers.