drivers: flash: flexspi_mx25um51345g: fix DDR dummy cycles and correct max speed #97040
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In the DDR LUT, the dummy cycles were not defined for READ_STATUS_REG and had a wrong value for READ. The default amount of dummy cycles on this chip are 20 (0x14). This means the LUT should contain the value of 0x28 (0x14*2) for DDR at these entries. Signed-off-by: Andre Heinemans <[email protected]>
Maximum speed is 200MHz according to the mx25um51345g datasheet. Signed-off-by: Andre Heinemans <[email protected]>
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The DDR LUT entry for ERASE_CHIP was configured with an incorrect kFLEXSPI_Command, resulting in the erase operation not being executed. Signed-off-by: Andre Heinemans <[email protected]>
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@AndreHeinemans-NXP which platform(s) did you see issues with? This driver has been in the tree for a while so curious how you identified these needed changes. Would like to coordinate with @hakehuang to confirm CI coverage. |
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@dleach02 The difference is maybe in the rx-clock-source setting. At first I had the driver configured with rx-clock-source='3 # External input from DQS pad'. With this setting the driver worked without a problem. But we encountered some issues with the DQS signal and for that reason I started using rx-clock-source='1 # Loopback from DQS pad'. With this setting the driver did not read the data correctly anymore as it requires the correct amount of dummy cycles in the lut. |
200M is quick challenging, let me run a regression, and feedback. |
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@hakehuang I am going to make this change and lower the spi-max-frequency for the boards that require 120MHz. Depending on the results of your tests. |
In the DDR LUT, the dummy cycles were not defined for READ_STATUS_REG and had a wrong value for READ. The default amount of dummy cycles on this chip are 20 (0x14). This means the LUT should contain the value of 0x28 (0x14*2) for DDR
at these entries.
Maximum speed is 200MHz according to the mx25um51345g datasheet and is adjusted in the driver code accordingly.
Both changes were tested with an imx95 m7 connected to a mx25um51345g.
edit: Just discovered that the ERASE_CHIP DDR entry in the LUT was also incorrect. I put the fix for that in this PR as well.