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drivers: flash: flexspi_mx25um51345g: fix DDR dummy cycles and correct max speed #97040

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drivers: flash: flexspi_mx25um51345g: fix DDR dummy cycles and correct max speed #97040

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2eaf520
drivers: flash: flexspi_mx25um51345g: fix DDR dummy cycles
AndreHeinemans-NXP Oct 2, 2025
8a74463
drivers: flash: flexspi_mx25um51345g: get max speed from dts
AndreHeinemans-NXP Aug 12, 2025
be412ef
drivers: flash: flexspi_mx25um51345g: fix erase chip lut entry
AndreHeinemans-NXP Oct 6, 2025
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2 changes: 1 addition & 1 deletion boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -400,7 +400,7 @@ zephyr_udc0: &usbhs {
/* MX25UM51245G is 64MB, 512MBit flash part */
size = <DT_SIZE_M(64 * 8)>;
reg = <0>;
spi-max-frequency = <DT_FREQ_M(200)>;
spi-max-frequency = <DT_FREQ_M(120)>;
status = "okay";
jedec-id = [c2 81 3a];
erase-block-size = <DT_SIZE_K(4)>;
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2 changes: 1 addition & 1 deletion boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts
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Expand Up @@ -265,7 +265,7 @@ i2s1: &flexcomm3 {
/* MX25UM51245G is 64MB, 512MBit flash part */
size = <DT_SIZE_M(64 * 8)>;
reg = <2>;
spi-max-frequency = <DT_FREQ_M(200)>;
spi-max-frequency = <DT_FREQ_M(120)>;
status = "okay";
jedec-id = [c2 81 3a];
erase-block-size = <DT_SIZE_K(4)>;
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2 changes: 1 addition & 1 deletion boards/nxp/vmu_rt1170/vmu_rt1170.dtsi
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Expand Up @@ -205,7 +205,7 @@
/* MX25UM51245G is 64MB, 512MBit flash part */
size = <DT_SIZE_M(64 * 8)>;
reg = <0>;
spi-max-frequency = <DT_FREQ_M(200)>;
spi-max-frequency = <DT_FREQ_M(120)>;
status = "okay";
jedec-id = [c2 81 3a];
erase-block-size = <DT_SIZE_K(4)>;
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12 changes: 8 additions & 4 deletions drivers/flash/flash_mcux_flexspi_mx25um51345g.c
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Original file line number Diff line number Diff line change
Expand Up @@ -105,6 +105,7 @@ static const uint32_t flash_flexspi_nor_lut[][4] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_8PAD, 0x04,
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
},

[WRITE_ENABLE_OPI] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x06,
kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xF9),
Expand Down Expand Up @@ -142,7 +143,9 @@ static const uint32_t flash_flexspi_nor_lut[][4] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05,
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xFA),
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x4),
kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x28),
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x4,
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
},

[WRITE_ENABLE_OPI] = {
Expand All @@ -159,14 +162,14 @@ static const uint32_t flash_flexspi_nor_lut[][4] = {

[ERASE_CHIP] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60,
kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x9F),
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F),
},

[READ] = {
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xEE,
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x11),
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x08),
kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x28),
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04,
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
},
Expand Down Expand Up @@ -597,7 +600,8 @@ static DEVICE_API(flash, flash_flexspi_nor_api) = {

#define FLASH_FLEXSPI_DEVICE_CONFIG(n) \
{ \
.flexspiRootClk = MHZ(120), \
.flexspiRootClk = \
DT_INST_PROP_OR(n, spi_max_frequency, MHZ(200)),\
.flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \
.CSIntervalUnit = \
CS_INTERVAL_UNIT( \
Expand Down