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This update add clock control driver for the PIC32CM-JH SoC family, providing bindings for a range of clock sources and generators including OSC48M, FDPLL, GCLK generator, MCLK CPU, XOSC32K, OSC32K, RTC clock, and XOSC.

The driver now supports bootup clock initialization, APIs for clock on/off, get status, get rate, and dynamic clock configuration.
The board configuration has been updated to set the CPU clock to 48 MHz by using the FDPLL, which is sourced from XOSC.

Add bindings for dfll, fdpll, gclk generator, mclk cpu, osc32k, rtc clock
and xosc.

Signed-off-by: Sunil Abraham <[email protected]>
@sunil-abraham sunil-abraham force-pushed the pic32cm_jh_clock_control_driver branch 2 times, most recently from 8816588 to 477ce0d Compare October 9, 2025 05:11
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sonarqubecloud bot commented Oct 9, 2025

Add clock control driver.
Implement bootup clock initialization, on, off and get_rate API.

Signed-off-by: Sunil Abraham <[email protected]>
Configure CPU clock using FDPLL, sourced from XOSC to achieve 48Mhz.

Signed-off-by: Sunil Abraham <[email protected]>
@sunil-abraham sunil-abraham force-pushed the pic32cm_jh_clock_control_driver branch from 477ce0d to 04b546b Compare October 9, 2025 05:54
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