drivers: clock: PIC32CM-JH: add clock control driver

boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.dts

@@ -56,5 +56,71 @@
 };
 
 &cpu0 {
-	clock-frequency = <4000000>;
+	clock-frequency = <48000000>;
+};
+
+&clock {
+	compatible = "microchip,pic32cm-jh-clock";
+
+	/* If cpu sourced from osc48m, use 3 for CPU frequency above 24Mhz */
+	flash-wait-states = <2>;
+
+	xosc: xosc {
+		compatible = "microchip,pic32cm-jh-xosc";
+		xosc-frequency = <32000000>;
+		xosc-en = <1>;
+		xosc-xtal-en = <1>;
+		xosc-run-in-standby-en = <1>;
+	};
+
+	fdpll: fdpll {
+		compatible = "microchip,pic32cm-jh-fdpll";
+		fdpll-xosc-clock-divider = <15>;
+		fdpll-divider-ratio-frac = <0>;
+		fdpll-divider-ratio-int = <95>;
+		fdpll-output-prescalar = "div2";
+		fdpll-src = "xosc";
+		fdpll-run-in-standby-en = <1>;
+		fdpll-en = <1>;
+	};
+
+	xosc32k: xosc32k {
+		compatible = "microchip,pic32cm-jh-xosc32k";
+		xosc32k-32khz-en = <1>;
+		xosc32k-xtal-en = <1>;
+		xosc32k-startup-time = "122-us";
+		xosc32k-run-in-standby-en = <1>;
+		xosc32k-en = <1>;
+	};
+
+	osc32k: osc32k {
+		compatible = "microchip,pic32cm-jh-osc32k";
+		osc32k-32khz-en = <1>;
+		osc32k-startup-time = "183-us";
+		osc32k-run-in-standby-en = <1>;
+		osc32k-en = <0>;
+	};
+
+	gclkgen: gclkgen {
+		compatible = "microchip,pic32cm-jh-gclkgen";
+
+		gclkgen0 {
+			subsystem = <CLOCK_MCHP_GCLKGEN_ID_GEN0>;
+			gclkgen-div-factor = <1>;
+			gclkgen-run-in-standby-en = <1>;
+			gclkgen-src = "fdpll";
+			gclkgen-en = <1>;
+		};
+	};
+
+	gclkperiph: gclkperiph {
+		compatible = "microchip,pic32cm-jh-gclkperiph";
+		#clock-cells = <1>;
+
+		sercom2 {
+			subsystem = <CLOCK_MCHP_GCLKPERIPH_ID_SERCOM4_CORE>;
+			gclkperiph-src = "gclk0";
+			gclkperiph-en = <1>;
+		};
+	};
 };

drivers/clock_control/CMakeLists.txt

@@ -10,6 +10,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_FIXED_RATE_CLOCK    clock_cont
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_GD32                clock_control_gd32.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX               clock_control_litex.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LPC11U6X            clock_control_lpc11u6x.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_PIC32CM_JH     clock_control_mchp_pic32cm_jh.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_SAM_D5X_E5X    clock_control_mchp_sam_d5x_e5x.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_XEC            clock_control_mchp_xec.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_CCM            clock_control_mcux_ccm.c)

drivers/clock_control/Kconfig.mchp

@@ -2,25 +2,59 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config CLOCK_CONTROL_MCHP_COMMON
-	bool
+	bool  "Microchip clock controller"
 	help
 	  Common options for Microchip clock control drivers.
 
 config CLOCK_CONTROL_MCHP_SAM_D5X_E5X
-	bool "Microchip SAM D5X/E5X clock controller Support"
+	bool
 	depends on DT_HAS_MICROCHIP_SAM_D5X_E5X_CLOCK_ENABLED
 	default y
 	select CLOCK_CONTROL_MCHP_COMMON
 	help
 	  Enable clock controller driver for Microchip SAM D5X/E5X SoC family.
 
+config CLOCK_CONTROL_MCHP_PIC32CM_JH
+	bool
+	default y
+	depends on DT_HAS_MICROCHIP_PIC32CM_JH_CLOCK_ENABLED
+	select CLOCK_CONTROL_MCHP_COMMON
+	help
+	  Enable clock controller driver for Microchip PIC32CM_JH family.
+
 if CLOCK_CONTROL_MCHP_COMMON
 
+config CLOCK_CONTROL_MCHP_CONFIG_BOOTUP
+	bool "Bootup clock configuration"
+	default y
+	help
+	  This option enables bootup clock configuration from device tree node.
+
+config CLOCK_CONTROL_MCHP_CONFIG_RUNTIME
+	bool "Runtime clock configuration"
+	default y
+	help
+	  This option enables runtime clock configuration using API.
+
+config CLOCK_CONTROL_MCHP_ASYNC_ON
+	bool "Async clock on"
+	default n
+	help
+	  This option enables async on API.
+
 config CLOCK_CONTROL_MCHP_GET_RATE
 	bool "Get clock rate"
 	default y
 	help
 	  Enable support for retrieving the clock rate. This may increase
 	  code size, depending on the depth of clock source hierarchy.
 
+config CLOCK_CONTROL_MCHP_SET_RATE
+	bool "Set clock rate"
+	default n
+	depends on CLOCK_CONTROL_MCHP_GET_RATE
+	help
+	  This option enables set rate API. This may increase
+	  code size, depending on the depth of clock source hierarchy.
+
 endif # CLOCK_CONTROL_MCHP_COMMON