Adding dave2d driver support on lvgl for Renesas RA devices

boards/renesas/ek_ra8d1/Kconfig.defconfig

@@ -30,6 +30,9 @@ if LVGL
 config LV_Z_VDB_CUSTOM_SECTION
 	default y
 
+config LV_ATTRIBUTE_MEM_ALIGN_SIZE
+	default 4
+
 endif # LVGL
 
 endif # BOARD_EK_RA8D1

boards/renesas/ek_ra8d1/ek_ra8d1.dts

@@ -537,6 +537,12 @@ dvp_20pin_interface: &ceu {};
 	};
 };
 
+&drw {
+	interrupts = <90 12>;
+	interrupt-names = "drw";
+	status = "okay";
+};
+
 &crc {
 	status = "okay";
 };

boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts

@@ -130,6 +130,12 @@
 	burst-transfer = <256>;
 };
 
+&drw {
+	interrupt-names = "drw";
+	interrupts = <23 12>;
+	status = "okay";
+};
+
 zephyr_lcdif: &lcdif {};
 
 pmod_sd_shield: &sdhc0 {};

boards/shields/rtklcdpar1s00001be/boards/ek_ra8p1_r7ka8p1kflcac_cm85.defconfig

@@ -19,6 +19,9 @@ if LVGL
 config LV_Z_VDB_CUSTOM_SECTION
 	default y
 
+config LV_ATTRIBUTE_MEM_ALIGN_SIZE
+	default 4
+
 endif # LVGL
 
 endif # BOARD_EK_RA8P1

boards/shields/rtklcdpar1s00001be/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay

@@ -65,9 +65,13 @@
 	interrupt-names = "line";
 	pinctrl-0 = <&glcdc_default>;
 	pinctrl-names = "default";
-	output-pin-hsync = "TCON_PIN_1";
-	output-pin-vsync = "TCON_PIN_0";
+	output-pin-hsync = "TCON_PIN_NONE";
+	output-pin-vsync = "TCON_PIN_NONE";
 	output-pin-de = "TCON_PIN_2";
+	output-clock-divisor = <4>;
+	def-back-color-red = <0>;
+	def-back-color-green = <0>;
+	def-back-color-blue = <0>;
 };
 
 &iic1 {

boards/shields/rtklcdpar1s00001be/rtklcdpar1s00001be.overlay

@@ -37,15 +37,15 @@
 
 	display-timings {
 		compatible = "zephyr,panel-timing";
-		hsync-len = <1>;
-		hback-porch = <140>;
-		vsync-len = <1>;
-		vback-porch = <20>;
+		hsync-len = <4>;
+		hback-porch = <160>;
+		vsync-len = <3>;
+		vback-porch = <23>;
 		hsync-active = <0>;
 		vsync-active = <0>;
 		de-active = <1>;
 		pixelclk-active = <0>;
-		hfront-porch = <179>;
-		vfront-porch = <403>;
+		hfront-porch = <156>;
+		vfront-porch = <9>;
 	};
 };

drivers/misc/CMakeLists.txt

@@ -14,5 +14,6 @@ add_subdirectory_ifdef(CONFIG_RENESAS_RA_EXTERNAL_INTERRUPT renesas_ra_external_
 add_subdirectory_ifdef(CONFIG_RENESAS_RX_EXTERNAL_INTERRUPT renesas_rx_external_interrupt)
 add_subdirectory_ifdef(CONFIG_NXP_RTXXX_DSP_CTRL nxp_rtxxx_dsp_ctrl)
 add_subdirectory_ifdef(CONFIG_STM32N6_AXISRAM stm32n6_axisram)
+add_subdirectory_ifdef(CONFIG_RENESAS_DRW renesas_drw)
 
 add_subdirectory(interconn)

drivers/misc/Kconfig

@@ -21,5 +21,6 @@ source "drivers/misc/renesas_rx_external_interrupt/Kconfig"
 source "drivers/misc/nxp_rtxxx_dsp_ctrl/Kconfig"
 source "drivers/misc/stm32n6_axisram/Kconfig"
 source "drivers/misc/nxp_inputmux/Kconfig"
+source "drivers/misc/renesas_drw/Kconfig"
 
 endmenu

drivers/misc/renesas_drw/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources_ifdef(CONFIG_RENESAS_RA_DRW renesas_ra_drw.c)

drivers/misc/renesas_drw/Kconfig

@@ -0,0 +1,22 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Renesas DRW (D/AVE 2D) config options
+
+menuconfig RENESAS_DRW
+	bool "Renesas DRW Driver"
+	depends on SOC_FAMILY_RENESAS_RA
+	help
+	  Enable config options for Renesas DRW driver
+
+if RENESAS_DRW
+
+config RENESAS_DRW_INIT_PRIORITY
+	int "Renesas DRW initialization priority"
+	default KERNEL_INIT_PRIORITY_DEVICE
+	help
+	  System initialization priority for Renesas DRW drivers.
+
+source "drivers/misc/renesas_drw/Kconfig.renesas_ra_drw"
+
+endif # RENESAS_DRW

drivers/misc/renesas_drw/Kconfig.renesas_ra_drw

@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config RENESAS_RA_DRW
+	bool "Renesas RA DRW Driver"
+	depends on DT_HAS_RENESAS_RA_DRW_ENABLED
+	select USE_RA_FSP_DRW
+	default y
+	help
+	  Enable config options for Renesas DRW driver
+
+if RENESAS_RA_DRW
+config RENESAS_DAVE2D_RUNTIME_HEAP_SIZE
+	int "Renesas DAVE2D runtime heap size"
+	default 8192
+	help
+	  Set the size of the runtime heap for DAVE2D driver.
+	  This heap is used for dynamic memory allocation during runtime.
+
+endif # RENESAS_RA_DRW

drivers/misc/renesas_drw/renesas_ra_drw.c

@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_ra_drw
+
+#include <zephyr/kernel.h>
+#include <zephyr/irq.h>
+#include <soc.h>
+#include <r_drw_base.h>
+#include <r_drw_cfg.h>
+
+#define DRW_PRV_IRQCTL_DLISTIRQ_ENABLE BIT(1)
+#define DRW_PRV_IRQCTL_ENUMIRQ_CLEAR   BIT(2)
+#define DRW_PRV_IRQCTL_DLISTIRQ_CLEAR  BIT(3)
+#define DRW_PRV_IRQCTL_BUSIRQ_CLEAR    BIT(5)
+#define DRW_PRV_IRQCTL_ALLIRQ_DISABLE_AND_CLEAR                                                    \
+	(DRW_PRV_IRQCTL_BUSIRQ_CLEAR | DRW_PRV_IRQCTL_DLISTIRQ_CLEAR | DRW_PRV_IRQCTL_ENUMIRQ_CLEAR)
+#define DRW_PRV_IRQCTL_ALLIRQ_CLEAR_AND_DLISTIRQ_ENABLE                                            \
+	(DRW_PRV_IRQCTL_BUSIRQ_CLEAR | DRW_PRV_IRQCTL_DLISTIRQ_CLEAR |                             \
+	 DRW_PRV_IRQCTL_ENUMIRQ_CLEAR | DRW_PRV_IRQCTL_DLISTIRQ_ENABLE)
+#define DRW_PRV_STATUS_DLISTIRQ_TRIGGERED (1U << 5)
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(drw), okay)
+#define VECTOR_NUMBER_DRW_INT DT_IRQN(DT_NODELABEL(drw))
+#else
+#error "Device tree node 'drw' not found or disabled (status != okay)"
+#endif
+
+static struct k_sem d1_queryirq_sem;
+K_HEAP_DEFINE(drw_heap_runtime, CONFIG_RENESAS_DAVE2D_RUNTIME_HEAP_SIZE);
+
+d1_int_t d1_initirq_intern(d1_device_flex *handle)
+{
+	if (VECTOR_NUMBER_DRW_INT >= 0) {
+		/* Clear all the D/AVE 2D IRQs and enable Display list IRQ. */
+		R_FSP_IsrContextSet((IRQn_Type)VECTOR_NUMBER_DRW_INT, handle);
+		irq_enable(VECTOR_NUMBER_DRW_INT);
+		R_DRW->IRQCTL = DRW_PRV_IRQCTL_ALLIRQ_CLEAR_AND_DLISTIRQ_ENABLE;
+	}
+
+	return (k_sem_init(&d1_queryirq_sem, 0, 1) == 0);
+}
+
+d1_int_t d1_shutdownirq_intern(d1_device_flex *handle)
+{
+	ARG_UNUSED(handle);
+
+	/* Disable D/AVE 2D interrupt in NVIC. */
+	irq_disable(VECTOR_NUMBER_DRW_INT);
+
+	/* Clear all the D/AVE 2D IRQs and disable Display list IRQ. */
+	R_DRW->IRQCTL = DRW_PRV_IRQCTL_ALLIRQ_DISABLE_AND_CLEAR;
+
+	return 1;
+}
+
+d1_int_t d1_queryirq(d1_device *handle, d1_int_t irqmask, d1_int_t timeout)
+{
+	/* Wait for dlist processing to complete. */
+	return (k_sem_take(&d1_queryirq_sem, K_MSEC(timeout)) == 0);
+}
+
+void *d1_malloc(d1_uint_t size)
+{
+	return k_heap_alloc(&drw_heap_runtime, size, K_NO_WAIT);
+}
+
+void d1_free(void *ptr)
+{
+	k_heap_free(&drw_heap_runtime, ptr);
+}
+
+void drw_zephyr_irq_handler(const struct device *dev)
+{
+	uint32_t int_status;
+	IRQn_Type irq = R_FSP_CurrentIrqGet(); /* Get current IRQ number */
+
+	int_status = R_DRW->STATUS; /* Read D/AVE 2D interrupt status */
+	/* Clear all D/AVE 2D interrupts except for Display List IRQ enable */
+	R_DRW->IRQCTL = DRW_PRV_IRQCTL_ALLIRQ_CLEAR_AND_DLISTIRQ_ENABLE;
+
+	if (int_status & DRW_PRV_STATUS_DLISTIRQ_TRIGGERED) {
+		d1_device_flex *p_d1_handle = (d1_device_flex *)R_FSP_IsrContextGet(irq);
+
+		if (p_d1_handle != NULL) {
+			uint32_t **pp_dlist_indirect_start =
+				(uint32_t **)p_d1_handle->pp_dlist_indirect_start;
+			if (p_d1_handle->dlist_indirect_enable &&
+			    *pp_dlist_indirect_start != NULL) {
+				R_DRW->DLISTSTART = *pp_dlist_indirect_start;
+				p_d1_handle->pp_dlist_indirect_start++;
+			} else {
+				k_sem_give(&d1_queryirq_sem);
+			}
+		}
+	}
+	/* Clear IRQ status. */
+	R_BSP_IrqStatusClear(irq);
+}
+
+#define DRW_INIT(inst)                                                                             \
+	static int drw_renesas_ra_configure_func_##inst(void)                                      \
+	{                                                                                          \
+		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(inst, drw, irq)] = ELC_EVENT_DRW_INT;             \
+		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, drw, irq),                                   \
+			    DT_INST_IRQ_BY_NAME(inst, drw, priority), drw_zephyr_irq_handler,      \
+			    DEVICE_DT_INST_GET(inst), 0);                                          \
+		return 0;                                                                          \
+	}                                                                                          \
+	static int renesas_drw_init_##inst(const struct device *dev)                               \
+	{                                                                                          \
+		ARG_UNUSED(dev);                                                                   \
+		return drw_renesas_ra_configure_func_##inst();                                     \
+	}                                                                                          \
+	DEVICE_DT_INST_DEFINE(inst, renesas_drw_init_##inst, NULL, NULL, NULL, POST_KERNEL,        \
+			      CONFIG_RENESAS_DRW_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(DRW_INIT)

dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi

@@ -304,6 +304,12 @@
 			clocks = <&pclka MSTPC 16>;
 			status = "disabled";
 		};
+
+		drw: drw@40344000 {
+			compatible = "renesas,ra-drw";
+			reg = <0x40344000 0xD4>;
+			status = "disabled";
+		};
 	};
 
 	usbhs_phy: usbhs-phy {

dts/arm/renesas/ra/ra8/r7ka8p1kflcac.dtsi

@@ -59,5 +59,11 @@
 			clocks = <&lcdclk MSTPC 10>;
 			status = "disabled";
 		};
+
+		drw: drw@40444000 {
+			compatible = "renesas,ra-drw";
+			reg = <0x40444000 0xD4>;
+			status = "disabled";
+		};
 	};
 };

dts/bindings/misc/renesas,ra-drw.yaml

@@ -0,0 +1,12 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA DRW
+
+compatible: "renesas,ra-drw"
+
+include: base.yaml
+
+properties:
+  interrupts:
+    required: true

modules/Kconfig.renesas

@@ -243,6 +243,11 @@ config USE_RA_FSP_IPC
 	help
 	  Enable RA FSP IPC driver
 
+config USE_RA_FSP_DRW
+	bool
+	help
+	  Enable RA FSP DRW driver
+
 endif # HAS_RENESAS_RA_FSP
 
 if HAS_RENESAS_RZ_FSP

modules/lvgl/Kconfig

@@ -198,6 +198,10 @@ config LV_DRAW_DMA2D_HAL_INCLUDE
 	  Must be defined to include path of CMSIS header of target processor
 	  e.g. "stm32f769xx.h" or "stm32f429xx.h"
 
+config LV_USE_DRAW_DAVE2D
+	bool
+	imply RENESAS_DRW
+
 config LV_Z_USE_OSAL
 	bool "Use OSAL enabling parallel rendering"
 	depends on DYNAMIC_THREAD

samples/modules/lvgl/demos/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&flash0 {
+	reg = <0x2000000 0x100000>;
+};
+
+&flash1 {
+	status = "disabled";
+};

samples/modules/lvgl/demos/sample.yaml

@@ -69,6 +69,10 @@ tests:
     extra_args: SHIELD=rtkmipilcdb00000be
     tags:
       - shield
+    extra_configs:
+      - CONFIG_LV_Z_DEMO_WIDGETS=y
+      - CONFIG_LV_USE_SYSMON=y
+      - CONFIG_LV_USE_PERF_MONITOR=y
   sample.modules.lvgl.demos.rtk7eka6m3b00001bu:
     platform_allow: ek_ra8d1
     extra_args:
@@ -87,6 +91,8 @@ tests:
       - SHIELD=rtklcdpar1s00001be
       - DTC_OVERLAY_FILE=rtklcdpar1s00001be.overlay
     extra_configs:
-      - CONFIG_LV_DEMO_MUSIC_LANDSCAPE=y
+      - CONFIG_LV_Z_DEMO_WIDGETS=y
+      - CONFIG_LV_USE_SYSMON=y
+      - CONFIG_LV_USE_PERF_MONITOR=y
     tags:
       - shield

west.yml

@@ -226,7 +226,7 @@ manifest:
         - hal
     - name: hal_renesas
       path: modules/hal/renesas
-      revision: bc51c0b367223bb8f02a188e2e8529af0bd08f1c
+      revision: pull/154/head
       groups:
         - hal
     - name: hal_rpi_pico
@@ -313,7 +313,7 @@ manifest:
       revision: fb00b383072518c918e2258b0916c996f2d4eebe
       path: modules/lib/loramac-node
     - name: lvgl
-      revision: b03edc8e6282a963cd312cd0b409eb5ce263ea75
+      revision: pull/67/head
       path: modules/lib/gui/lvgl
     - name: mbedtls
       revision: 85440ef5fffa95d0e9971e9163719189cf34d979