drivers: flash: stm32_qspi: Correct special behaviour for Microchip QSPI flash memories #97211
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Commit 539928d introduced a special behaviour for Microchip QSPI flash memories into the STM32 QSPI flash driver, to handle the fact that these memories use the PP_1_1_4 opcode (32H) for the PP_1_4_4 operation (usually 38H). The special Microchip-specific behaviour introduced in that commit sets the address mode for a QSPI 1-1-4 write operation to 4 address lines, rather than 1 address line, when the write command is configured as SPI_NOR_CMD_PP_1_1_4. If the write command is configured as SPI_NOR_CMD_PP_1_4_4, nothing is done and the operation will not succeed. This behaviour is a bit backwards, as it results in a QSPI flash memory configured in 1-1-4 write mode using 4 address lines (1-4-4 operation). It should be the other way round, so that a QSPI flash memory configured in 1-4-4 mode uses 4 address lines (1-4-4 operation). This commit changes the Microchip-specific special behaviour to set the opcode for the specified write mode, rather than using a different write mode to that which is configured in order to use a valid opcode. This means that a QSPI flash memory configured in 1-4-4 mode, or without the writeoc DT property set (defaults to 1-4-4 for quad mode), will operate in 1-4-4 mode. 1-1-4 mode is unsupported, as before. Also update the Kconfig option description for CONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32 to remove references to the Global Block Protection Unlock instruction - this was added at the same time as the Microchip-specific special behaviour for the 1-1-4 / 1-4-4 opcode but is distinct from this and is not affected by CONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32. Signed-off-by: Ben Marsh <[email protected]>
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Commit 539928d introduced a special behaviour for Microchip QSPI flash memories into the STM32 QSPI flash driver, to handle the fact that these memories use the PP_1_1_4 opcode (32H) for the PP_1_4_4 operation (usually 38H).
The special behaviour is a bit backwards, as it results in a QSPI flash memory configured in 1-1-4 write mode using 4 address lines (1-4-4 operation). It should be the other way round, so that a QSPI flash memory configured in 1-4-4 mode uses 4 address lines (1-4-4 operation).
After these changes, the mode used matches the mode configured.
See commit message for more detailed explanation.
Before/After Comparison
Before:
Devicetree configuration requires
writeoc = "PP_1_1_4";for successful quad write, which then uses 1-4-4 mode.writeocpropertyAfter:
Devicetree configuration requires
writeoc = "PP_1_4_4";(or property omitted, defaults to 1-4-4 mode for quad mode) for successful quad write, which then uses 1-4-4 mode.writeocpropertyThis PR also updates the Kconfig option description for
CONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32to remove references to the Global Block Protection Unlock instruction - this was added at the same time as the Microchip-specific special behaviour for the 1-1-4 / 1-4-4 opcode but is distinct from this and is not affected byCONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32.