soc: ti_k3: am6x: enable cache for R5 cores #97264
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Enable cache during soc early init for Cortex-R5F cores in the TI AM6x series. Signed-off-by: Amneesh Singh <[email protected]>
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platform: TI K3
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Enable I-Cache and D-Cache during soc early init for Cortex-R5F cores in the TI AM6x series.