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soc: ti_k3: am6x: enable cache for R5 cores #97264

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soc: ti_k3: am6x: enable cache for R5 cores #97264

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6 changes: 6 additions & 0 deletions soc/ti/k3/am6x/r5/soc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
#include <zephyr/fatal.h>

#include "soc.h"
#include <zephyr/cache.h>
#include <common/ctrl_partitions.h>

unsigned int z_soc_irq_get_active(void)
Expand Down Expand Up @@ -51,5 +52,10 @@ int z_soc_irq_is_enabled(unsigned int irq)

void soc_early_init_hook(void)
{
sys_cache_data_disable();
sys_cache_instr_disable();
sys_cache_data_enable();
sys_cache_instr_enable();

k3_unlock_all_ctrl_partitions();
}