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This is a Draft PR test for Elan em32f967 SOC.

This is a SOC based on ARM.

Signed-off-by: Johnny Chuang <[email protected]>
This is a development board for Elan em32f967 SOC.

Signed-off-by: Johnny Chuang <[email protected]>
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Hello @ElanJohnnyChuang, and thank you very much for your first pull request to the Zephyr project!
Our Continuous Integration pipeline will execute a series of checks on your Pull Request commit messages and code, and you are expected to address any failures by updating the PR. Please take a look at our commit message guidelines to find out how to format your commit messages, and at our contribution workflow to understand how to update your Pull Request. If you haven't already, please make sure to review the project's Contributor Expectations and update (by amending and force-pushing the commits) your pull request if necessary.
If you are stuck or need help please join us on Discord and ask your question there. Additionally, you can escalate the review when applicable. 😊

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reg = <0x20000000 DT_SIZE_K(448)>;
};

clocks {
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this file is not formatted correctly

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This draft PR update is mainly for me to get familiar with the workflow. I’m aware that the current code still has many aspects that don’t meet the requirements. I will address those based on your suggestions and the issues reported by the CI pipeline. After the necessary fixes and optimizations, I’ll force‑push the changes to this PR and then convert the draft PR into a regular PR for your review. Thank you.

default 64

config SYS_CLOCK_HW_CYCLES_PER_SEC
default 60000000
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get from dt function from dts

HCLKF_GHM_M2D = 0x2b,
PCLKG_SSP1 = 0x30,
PCLKG_ALL = 0xffff
} CLKGatingSwitch;
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zephyr is snake case not camel case

#include "em32f967.h"
#include "soc_967.h"

extern const struct device __device_dts_ord_DT_CHOSEN_zephyr_cortex_m_idle_timer_ORD;
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no

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2 participants