MSPM0 MSPM0G51xx support

boards/ti/lp_mspm0g5187/Kconfig.lp_mspm0g5187

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Texas Instruments
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_LP_MSPM0G5187
+	select SOC_MSPM0G5187

boards/ti/lp_mspm0g5187/board.cmake

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=MSPM0G5187" "--speed=4000")
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/ti/lp_mspm0g5187/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: lp_mspm0g5187
+  full_name: MSPM0G5187 Launchpad
+  vendor: ti
+  socs:
+    - name: mspm0g5187

boards/ti/lp_mspm0g5187/doc/index.rst

@@ -0,0 +1,140 @@
+.. zephyr:board:: lp_mspm0g5187
+
+Overview
+********
+
+MSPM0G511x microcontrollers (MCUs) are part of the MSP highly integrated, ultra-low-power 32-bit MCU
+family based on the enhanced Arm® Cortex®-M0+ 32-bit core platform, operating at up to 80-MHz frequency.
+These MCUs offer a blend of cost optimization and design flexibility for applications requiring 32KB to 128KB
+of flash memory in small packages (down to 4 mm x 4 mm) or high pin count packages (up to 64 pins).
+These devices include USB 2.0-FS interface, digital audio interface, cybersecurity enablers, high performance
+integrated analog, and provide excellent low power performance across the operating temperature range.
+
+Hardware
+********
+
+The MSPM0G51xx devices provide up to 128KB embedded flash program memory with built-in error correction
+code (ECC) and up to 32KB SRAM with a hardware parity option. These MCUs also incorporate a
+memory protection unit, 12-channel DMA, and a variety of peripherals including
+
+* Analog.
+
+  * One 12-bit 4-Msps ADCs.
+
+  * Configurable internal shared voltage reference.
+
+  * One high speed comparator with built-in reference DAC.
+
+* Digital.
+
+  * Two 16-bit advanced control timers.
+
+  * Four general-purpose timers.
+
+    * Two 16-bit general-purpose timers.
+
+    * One 16-bit general-purpose timer with low-power operation in STANDBY mode.
+
+    * One 16-bit timer with deadband support and up to 8 PWM Channels.
+
+  * One basic software timer including 4 indenpendent configurable 16-bit counters.
+
+  * Two windowed-watchdog timers.
+
+  * One RTC with alarm and calendar modes.
+
+* Data Integrity and Encryption.
+
+  * One AES HW accelerator capable of CTR and CBC modes.
+
+  * One Cyclic Redundancy Check (CRC) accelerator.
+
+* Communication.
+
+  * Two configurable serial interfaces (UNICOMM) supporting UART or I2C.
+
+  * One configurable serial interface supporting UART or SPI.
+
+  * One dedicated SPI interface up to 32 Mbits/s.
+
+  * One digital audio interface (I2S) supporting controller and target mode.
+
+  * One USB2.0 interface with full-speed (12-Mbps) compliant device and host mode.
+
+Zephyr uses the ``lp_mspm0g5187`` board for building LP_MSPM0G5187
+
+Features
+********
+
+- Onboard XDS110 debug probe
+- EnergyTrace technology available for ultra-low-power debugging
+- 3 buttons, 1 LED and 1 RGB LED for user interaction
+- One microSD slot
+- One microphone
+- One I2S based audio ADC
+
+Details on the MSPM0G5187 LaunchPad can be found on the `TI LP_MSPM0G5187 Product Page`_.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Building and Flashing
+*********************
+
+Building
+========
+
+Follow the :ref:`getting_started` instructions for Zephyr application development.
+
+For example, to build the blinky application for the MSPM0G5187 LaunchPad:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: lp_mspm0g5187
+   :goals: build
+
+The resulting ``zephyr.bin`` binary in the build directory can be flashed onto
+MSPM0G5187 LaunchPad using the steps mentioned below.
+
+Flashing
+========
+
+OpenOCD can be used to program the flash memory on the devices.
+
+.. code-block:: console
+
+   $ west flash --openocd <path to cloned dir>/src/openocd --openocd-search <path to cloned dir>/tcl
+
+Flashing can also be done using JLINK.
+
+.. code-block:: console
+
+   $ west flash --runner jlink
+
+Debugging
+=========
+
+You can debug an application in the usual way. Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: lp_mspm0g5187
+   :goals: debug
+
+References
+**********
+
+- `TI MSPM0 MCU Page`_
+- `MSPM0G5187 TRM`_
+
+.. _TI MSPM0 MCU Page:
+   https://www.ti.com/microcontrollers-mcus-processors/arm-based-microcontrollers/arm-cortex-m0-mcus/overview.html
+
+.. _MSPM0G5187 TRM:
+   https://www.ti.com/lit/slau846
+
+.. _TI LP_MSPM0G5187 Product Page:
+   https://www.ti.com/tool/LP-MSPM0G5187

boards/ti/lp_mspm0g5187/lp_mspm0g5187.dts

@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+/dts-v1/;
+
+#include <ti/mspm0/g/mspm0g5187.dtsi>
+#include <ti/mspm0/g/mspm0g51xx-pinctrl.dtsi>
+#include <zephyr/dt-bindings/clock/mspm0_clock.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "TI LP_MSPM0G5117";
+	compatible = "ti,mspm0g5117";
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		sw0 = &btn0;
+		sw1 = &btn1;
+		uart0 = &unicomm0_uart;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &unicomm0_uart;
+		zephyr,shell-uart = &unicomm0_uart;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0: led_0 {
+			gpios = <&gpiob 13 GPIO_ACTIVE_HIGH>;
+			label = "Blue LED";
+		};
+		led1: led_1 {
+			gpios = <&gpioa 17 GPIO_ACTIVE_HIGH>;
+			label = "Red LED";
+		};
+		led2: led_2 {
+			gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>;
+			label = "Green LED";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		btn0: btn_0 {
+			gpios = <&gpiob 21 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			label = "Switch 3";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+		btn1: btn_1 {
+			gpios = <&gpioa 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			label = "Switch 2";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <DT_FREQ_M(80)>;
+};
+
+&ulpclk {
+	clock-frequency = <DT_FREQ_M(40)>;
+	clk-div = <2>;
+};
+
+&mclk {
+	clock-frequency = <DT_FREQ_M(80)>;
+	clocks = <&hsclk 0>;
+};
+
+&hsclk {
+	clocks = <&syspll2x 0>;
+	status = "okay";
+};
+
+&syspll2x {
+	status = "okay";
+};
+
+&flash0 {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 0x8000>;
+		};
+
+		slot0_partition: partition@8000 {
+			label = "image-0";
+			reg = <0x00008000 0x8000>;
+		};
+
+		slot1_partition: partition@10000 {
+			label = "image-1";
+			reg = <0x00010000 0x8000>;
+		};
+
+		storage_partition: partition@18000 {
+			label = "storage";
+			reg = <0x00018000 0x8000>;
+		};
+	};
+};
+
+&pinctrl {
+	status = "okay";
+};
+
+&gpioa {
+	status = "okay";
+};
+
+&gpiob {
+	status = "okay";
+};
+
+&unicomm0_uart {
+	compatible = "ti,mspm0-uart";
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uc0_tx_pa10 &uc0_rx_pa11>;
+	pinctrl-names = "default";
+};

boards/ti/lp_mspm0g5187/lp_mspm0g5187.yaml

@@ -0,0 +1,14 @@
+identifier: lp_mspm0g5187
+name: TI MSPM0G5187 Launchpad
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+ram: 32
+flash: 128
+supported:
+  - uart
+  - gpio
+vendor: ti

boards/ti/lp_mspm0g5187/lp_mspm0g5187_defconfig

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_CLOCK_CONTROL=y

boards/ti/lp_mspm0g5187/support/openocd.cfg

@@ -0,0 +1,4 @@
+source [find interface/xds110.cfg]
+adapter speed 10000
+
+source [find target/ti_mspm0.cfg]

drivers/gpio/gpio_mspm0.c

@@ -39,6 +39,17 @@ struct gpio_mspm0_data {
 #if CONFIG_SOC_SERIES_MSPM0G
 #define NUM_GPIOA_PIN 32
 #define gpioa_pins    NUM_GPIOA_PIN
+#if CONFIG_SOC_MSPM0G5187
+static uint8_t gpioa_pincm_lut[NUM_GPIOA_PIN] = {
+	IOMUX_PINCM1,  IOMUX_PINCM2, IOMUX_PINCM3,  IOMUX_PINCM4,
+	IOMUX_PINCM5, IOMUX_PINCM6, IOMUX_PINCM7,  IOMUX_PINCM8,  IOMUX_PINCM9,
+	IOMUX_PINCM10, IOMUX_PINCM11, IOMUX_PINCM14, IOMUX_PINCM19, IOMUX_PINCM20,
+	IOMUX_PINCM21, IOMUX_PINCM22, IOMUX_PINCM34, IOMUX_PINCM35, IOMUX_PINCM36,
+	IOMUX_PINCM37, IOMUX_PINCM38, IOMUX_PINCM39, IOMUX_PINCM40, IOMUX_PINCM41,
+	IOMUX_PINCM42, IOMUX_PINCM46, IOMUX_PINCM47, IOMUX_PINCM53, IOMUX_PINCM54,
+	IOMUX_PINCM55, IOMUX_PINCM58, IOMUX_PINCM59
+};
+#else
 static uint8_t gpioa_pincm_lut[NUM_GPIOA_PIN] = {
 	IOMUX_PINCM1,  IOMUX_PINCM2,  IOMUX_PINCM7,  IOMUX_PINCM8,  IOMUX_PINCM9,  IOMUX_PINCM10,
 	IOMUX_PINCM11, IOMUX_PINCM14, IOMUX_PINCM19, IOMUX_PINCM20, IOMUX_PINCM21, IOMUX_PINCM22,
@@ -47,6 +58,7 @@ static uint8_t gpioa_pincm_lut[NUM_GPIOA_PIN] = {
 	IOMUX_PINCM54, IOMUX_PINCM55, IOMUX_PINCM59, IOMUX_PINCM60, IOMUX_PINCM3,  IOMUX_PINCM4,
 	IOMUX_PINCM5,  IOMUX_PINCM6,
 };
+#endif
 #elif CONFIG_SOC_SERIES_MSPM0L /* if CONFIG_SOC_SERIES_MSPM0L */
 #define GPIOA_NODE DT_NODELABEL(gpioa)
 #define NUM_GPIOA_PIN 31
@@ -69,13 +81,24 @@ static uint8_t gpioa_pincm_lut[NUM_GPIOA_PIN] = {
 #ifdef CONFIG_SOC_SERIES_MSPM0G
 #define NUM_GPIOB_PIN 28
 #define gpiob_pins    NUM_GPIOB_PIN
+#if CONFIG_SOC_MSPM0G5187
+static uint8_t gpiob_pincm_lut[NUM_GPIOB_PIN] = {
+	IOMUX_PINCM12, IOMUX_PINCM13, IOMUX_PINCM15, IOMUX_PINCM16, IOMUX_PINCM17,
+	IOMUX_PINCM18, IOMUX_PINCM23, IOMUX_PINCM24, IOMUX_PINCM25, IOMUX_PINCM26,
+	IOMUX_PINCM27, IOMUX_PINCM28, IOMUX_PINCM29, IOMUX_PINCM30, IOMUX_PINCM31,
+	IOMUX_PINCM32, IOMUX_PINCM33, IOMUX_PINCM43, IOMUX_PINCM44, IOMUX_PINCM45,
+	IOMUX_PINCM48, IOMUX_PINCM49, IOMUX_PINCM50, IOMUX_PINCM51, IOMUX_PINCM52,
+	IOMUX_PINCM56
+};
+#else
 static uint8_t gpiob_pincm_lut[NUM_GPIOB_PIN] = {
 	IOMUX_PINCM12, IOMUX_PINCM13, IOMUX_PINCM15, IOMUX_PINCM16, IOMUX_PINCM17, IOMUX_PINCM18,
 	IOMUX_PINCM23, IOMUX_PINCM24, IOMUX_PINCM25, IOMUX_PINCM26, IOMUX_PINCM27, IOMUX_PINCM28,
 	IOMUX_PINCM29, IOMUX_PINCM30, IOMUX_PINCM31, IOMUX_PINCM32, IOMUX_PINCM33, IOMUX_PINCM43,
 	IOMUX_PINCM44, IOMUX_PINCM45, IOMUX_PINCM48, IOMUX_PINCM49, IOMUX_PINCM50, IOMUX_PINCM51,
 	IOMUX_PINCM52, IOMUX_PINCM56, IOMUX_PINCM57, IOMUX_PINCM58,
 };
+#endif
 #elif CONFIG_SOC_SERIES_MSPM0L /* if CONFIG_SOC_SERIES_MSPM0L */
 #define GPIOB_NODE DT_NODELABEL(gpiob)
 #define NUM_GPIOB_PIN 32

drivers/serial/Kconfig.mspm0

@@ -8,7 +8,8 @@ config UART_MSPM0
 	depends on DT_HAS_TI_MSPM0_UART_ENABLED
 	select SERIAL_HAS_DRIVER
 	select SERIAL_SUPPORT_INTERRUPT
-	select USE_MSPM0_DL_UART
+	select USE_MSPM0_DL_UNICOMM_UART if (HAS_MSP_UNICOMM)
+	select USE_MSPM0_DL_UART if !(HAS_MSP_UNICOMM)
 	select PINCTRL
 	help
 	  This option enables the TI MSPM0 UART driver.