stm32h745i_disco/stm32h750b_dk: fix instabilites in SDRAM access and full SDRAM access test

boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts

@@ -37,7 +37,8 @@
 	sdram2: sdram@d0000000 {
 		compatible = "zephyr,memory-region", "mmio-sram";
 		device_type = "memory";
-		reg = <0xd0000000 DT_SIZE_M(16)>; /* 128Mbit */
+		/* 128Mbit, but only half is available by HW design */
+		reg = <0xd0000000 DT_SIZE_M(8)>;
 		zephyr,memory-region = "SDRAM2";
 		zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>;
 	};
@@ -274,7 +275,7 @@
 					    STM32_FMC_SDRAM_MWID_16
 					    STM32_FMC_SDRAM_NB_4
 					    STM32_FMC_SDRAM_CAS_2
-					    STM32_FMC_SDRAM_SDCLK_PERIOD_2
+					    STM32_FMC_SDRAM_SDCLK_PERIOD_3
 					    STM32_FMC_SDRAM_RBURST_ENABLE
 					    STM32_FMC_SDRAM_RPIPE_0>;
 			st,sdram-timing = <2 7 4 7 2 2 2>;

boards/st/stm32h750b_dk/stm32h750b_dk-common.dtsi

@@ -20,7 +20,8 @@
 	sdram2: sdram@d0000000 {
 		compatible = "zephyr,memory-region", "mmio-sram";
 		device_type = "memory";
-		reg = <0xd0000000 DT_SIZE_M(16)>; /* 128Mbit */
+		/* 128Mbit, but only half is available by HW design */
+		reg = <0xd0000000 DT_SIZE_M(8)>;
 		zephyr,memory-region = "SDRAM2";
 		zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>;
 	};
@@ -236,7 +237,7 @@
 					    STM32_FMC_SDRAM_MWID_16
 					    STM32_FMC_SDRAM_NB_4
 					    STM32_FMC_SDRAM_CAS_3
-					    STM32_FMC_SDRAM_SDCLK_PERIOD_2
+					    STM32_FMC_SDRAM_SDCLK_PERIOD_3
 					    STM32_FMC_SDRAM_RBURST_ENABLE
 					    STM32_FMC_SDRAM_RPIPE_1>;
 			st,sdram-timing = <2 7 4 7 2 2 2>;

tests/drivers/memc/ram/boards/stm32f769i_disco.overlay

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Test the full SDRAM accesses. Discable LTDC to prevent conflicts */
+
+ram0: &sdram1 {};
+
+&ltdc {
+	status = "disabled";
+};

tests/drivers/memc/ram/boards/stm32h745i_disco_stm32h745xx_m7.overlay

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Test the full SDRAM accesses. Discable LTDC to prevent conflicts */
+
+ram0: &sdram2 {};
+
+&ltdc {
+	status = "disabled";
+};

tests/drivers/memc/ram/boards/stm32h747i_disco_stm32h747xx_m7.overlay

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Test the full SDRAM accesses. Discable LTDC to prevent conflicts */
+
+ram0: &sdram2 {};
+
+&ltdc {
+	status = "disabled";
+};

tests/drivers/memc/ram/boards/stm32h750b_dk.overlay

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Test the full SDRAM accesses. Discable LTDC to prevent conflicts */
+
+ram0: &sdram2 {};
+
+&ltdc {
+	status = "disabled";
+};

tests/drivers/memc/ram/src/main.c

@@ -15,24 +15,27 @@
 #define BUF_SIZE_SDRAM	64U
 #define BUF_SIZE_SRAM	64U
 
-#define BUF_DEF(label, size) static uint32_t buf_##label[size]		\
+#define BUF_DEF(label, size) static uint32_t buf_##label[(size) / sizeof(uint32_t)] \
 	Z_GENERIC_SECTION(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(label)))
 
 /**
  * @brief Helper function to test RAM r/w.
  *
  * @param mem RAM memory location to be tested.
  */
-static void test_ram_rw(uint32_t *mem, size_t size)
+static void test_ram_rw(uint32_t *mem, size_t size_byte)
 {
+	size_t size_32b = size_byte / sizeof(uint32_t);
+
 	/* fill memory with number range (0, BUF_SIZE - 1) */
-	for (size_t i = 0U; i < size / sizeof(uint32_t); i++) {
+	for (size_t i = 0U; i < size_32b; i++) {
 		mem[i] = i;
 	}
 
 	/* check that memory contains written range */
-	for (size_t i = 0U; i < size / sizeof(uint32_t); i++) {
-		zassert_equal(mem[i], i, "Unexpected content on byte %zd", i);
+	for (size_t i = 0U; i < size_32b; i++) {
+		zassert_equal(mem[i], i, "Unexpected content @%p: 0x%x != 0x%zx",
+			      mem + i, mem[i], i);
 	}
 }