ALU54D

This device is supported in Apicula.

Ports

Port	Size	Direction
A	54	input
ACCLOAD	1	input
ASIGN	1	input
B	54	input
BSIGN	1	input
CASI	55	input
CASO	55	output
CE	1	input
CLK	1	input
DOUT	54	output
RESET	1	input

Parameters

Parameter	Default Value
ACCLOAD_REG	0 (0b0)
ALUD_MODE	0 (0b00000000000000000000000000000000)
ALU_RESET_MODE	SYNC
AREG	0 (0b0)
ASIGN_REG	0 (0b0)
BREG	0 (0b0)
BSIGN_REG	0 (0b0)
B_ADD_SUB	0 (0b0)
C_ADD_SUB	0 (0b0)
OUT_REG	0 (0b0)

Verilog Instantiation

ALU54D #(
    .ACCLOAD_REG(ACCLOAD_REG),
    .ALUD_MODE(ALUD_MODE),
    .ALU_RESET_MODE(ALU_RESET_MODE),
    .AREG(AREG),
    .ASIGN_REG(ASIGN_REG),
    .BREG(BREG),
    .BSIGN_REG(BSIGN_REG),
    .B_ADD_SUB(B_ADD_SUB),
    .C_ADD_SUB(C_ADD_SUB),
    .OUT_REG(OUT_REG)
) alu54d_inst (
    .A(A),
    .ACCLOAD(ACCLOAD),
    .ASIGN(ASIGN),
    .B(B),
    .BSIGN(BSIGN),
    .CASI(CASI),
    .CASO(CASO),
    .CE(CE),
    .CLK(CLK),
    .DOUT(DOUT),
    .RESET(RESET)
);