Valence Semi RISC-V SoC v0.1.0

A clean-slate, open-source RISC-V SoC built for silicon. Configurable from YAML. Simulated in Verilator. Targeting real process nodes.

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Overview

Valence is a full RISC-V system-on-chip designed to go all the way to tape-out. The architecture is clean, the toolchain is open, and every physical parameter is derived from real PDK data — never guessed.

The SoC is parameterized through a structured YAML configuration system. One file describes your chip. Everything downstream — RTL parameters, elaboration, simulation — is generated from it.

Current status: OpenSBI v1.8.1 boots to completion in Verilator simulation. M-mode firmware initializes, enumerates platform devices, and attempts S-mode handoff. Active development is ongoing on HSM hart bring-up and the Linux boot path.

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Architecture

                    ┌─────────────────────────────────────┐
                    │           Valence SoC 0.1.0         │
                    │                                     │
                    │  ┌──────────┐    ┌───────────────┐  │
                    │  │  RISC-V  │    │   L1 I/D$     │  │
                    │  │  Core    │◄──►│   Cache       │  │
                    │  │ RV64IMA  │    └───────────────┘  │
                    │  └────┬─────┘                       │
                    │       │ TileLink / AXI              │
                    │  ┌────▼──────────────────────────┐  │
                    │  │         System Bus            │  │
                    │  └──┬─────────┬────────┬────────-┘  │
                    │     │         │        │            │
                    │  ┌──▼──┐  ┌───▼──┐  ┌──▼──┐         │
                    │  │CLINT│  │ UART │  │ ROM │         │
                    │  │PLIC │  │8250  │  │SRAM │         │
                    │  └─────┘  └──────┘  └─────┘         │
                    └─────────────────────────────────────┘

ISA: RV64IMA — integer, multiply, atomic
Privilege levels: M-mode, S-mode, U-mode
Timer: ACLINT MSWI + MTIMER @ 10 MHz
Console: 16550-compatible UART
Boot firmware: OpenSBI v1.8.1 (fw_jump)
Simulation: Verilator (C++ co-simulation)
Target PDKs: sky130, extensible to others

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Boot Status

Stage	Status
Reset vector → OpenSBI entry	✅ Working
OpenSBI platform init	✅ Working
UART console output	✅ Working
SBI extension enumeration	✅ Working
S-mode handoff (HSM)	🔧 In progress
Linux kernel boot	🔧 Planned

OpenSBI output from simulation:

OpenSBI v1.8.1-87-g547a5bbd
Platform Name             : Valence RISC-V SoC
Platform Features         : medeleg
Platform HART Count       : 1
Platform Timer Device     : aclint-mtimer @ 10000000Hz
Platform Console Device   : uart8250
Firmware Base             : 0x80000000
Firmware Size             : 577 KB
Runtime SBI Version       : 3.0

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Chip Configuration System

Every chip variant is defined by a single YAML file. The build system validates it against a schema, renders RTL parameters, and feeds them into the Chisel elaboration.

config/chips/your_chip.yaml          ← you edit this
        │
        ▼
scripts/generate_params_master.py    ← validates + renders
        │
        ▼
hardware/src/.../GeneratedParams.scala   ← auto-generated, never edit
        │
        ▼
sbt hardware/compile                 ← compile the chip

Provided configurations

Config	Purpose
config/chips/sim.yaml	Minimal, fast — for Verilator simulation
config/chips/sky130.yaml	Full-featured, real sky130 PDK parameters

Repository layout

config/
├── schema/
│   └── master_schema.yaml      # defines all valid params and legal ranges
├── chips/
│   ├── sim.yaml                # simulation target
│   └── sky130.yaml             # sky130 tape-out target
└── templates/
    └── CoreParams.scala        # Jinja2 template — structure only, no values

hardware/
└── src/.../params/
    └── GeneratedParams.scala   # output of generate_params_master.py

scripts/
└── generate_params_master.py   # validator + renderer

opensbi/                        # pre-built OpenSBI firmware
├── fw_jump.hex
└── valence.dtb

sim/
└── verilator/
    ├── sim_SoC.cpp             # top-level Verilator harness
    └── obj_dir/                # compiled simulation binary

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Quickstart

Dependencies

• Chisel / FIRRTL via sbt
• Verilator ≥ 5.0
• Python 3.10+ with pyyaml, jinja2, jsonschema
• riscv64-unknown-elf toolchain (for firmware)
• dtc (device tree compiler)

Simulate

# Generate params for simulation target
python3 scripts/generate_params_master.py config/chips/sim.yaml

# Elaborate RTL
sbt elaborate

# Build Verilator simulation
cd sim/verilator
make

# Run — boots OpenSBI
./obj_dir/sim_SoC \
  +hex=../../../opensbi/fw_jump.hex \
  +dtb=../../../opensbi/valence.dtb \
  +cycles=50000000

Targeting sky130

python3 scripts/generate_params_master.py config/chips/sky130.yaml && sbt elaborate

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Adding a Chip Variant

Copy the nearest existing config and edit it:

cp config/chips/sky130.yaml config/chips/my_chip.yaml

Every field is defined and documented in schema/master_schema.yaml. Edit your values, then generate and compile:

python3 scripts/generate_params_master.py config/chips/my_chip.yaml
sbt hardware/compile

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Adding a Process Node

Only add a process node when you have real PDK data. Do not guess physical parameters.

1. Add the node to master_schema.yaml under physical.node.allowed
2. Record real clock, voltage, and metal layer values with source citations in the schema notes
3. Create config/chips/v1_newnode.yaml with values derived from the PDK
4. Generate and elaborate to verify

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Design Rules

These are not guidelines — they are invariants the build system enforces.

• Never edit GeneratedParams.scala by hand. It is overwritten on every generate run.
• Never guess physical parameters. Every value in a chip config must come from real PDK documentation.
• CoreParams.scala defines structure only. It is a Jinja2 template. Do not add numerical values to it.
• Schema is the source of truth. If a parameter isn't in master_schema.yaml, it doesn't exist.

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Technical Report

A detailed technical report covering the SoC microarchitecture, memory map, CSR implementation, simulation methodology, and tape-out considerations is available in docs/valence_technical_report.pdf.

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Roadmap

• OpenSBI boot in Verilator
• UART console output
• ACLINT timer and IPI infrastructure
• HSM S-mode hart handoff
• Linux kernel boot (nommu or with MMU)
• PLIC interrupt routing
• sky130 place-and-route with OpenLane
• Formal verification of privilege transitions

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License

Apache 2.0 — see LICENSE.

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_{Valence Semiconductors}