RVY encodings matching latest 0.9.9 draft

[Alexander Richardson (arichardson)]

Matching the latest version of https://riscv.github.io/riscv-cheri/

[codecov]

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 96.78%. Comparing base (4644ba3) to head (ab32717).
⚠️ Report is 17 commits behind head on master.

Additional details and impacted files

@@            Coverage Diff             @@
##           master     #420      +/-   ##
==========================================
- Coverage   97.08%   96.78%   -0.30%     
==========================================
  Files          14       14              
  Lines         926      933       +7     
==========================================
+ Hits          899      903       +4     
- Misses         27       30       +3     

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[Alexander Richardson (arichardson)]

This supersedes #396 since I was not able to update that one.

[Tariq Kurd (tariqkurd-repo)]

This PR is missing rv_y_h for HLV.Y, HSV.Y
Also the naming is inconsistent - rv_a_y should be named ry_y_a

[Alexander Richardson (arichardson)]

This PR is missing rv_y_h for HLV.Y, HSV.Y Also the naming is inconsistent - rv_a_y should be named ry_y_a

I did not include HLV and HSV since those are not part of 1.0

[robinali-codasip]

Alexander Richardson (@arichardson) Tariq Kurd (@tariqkurd-repo) Should the CHERI memory instructions all have type rs1_n0 as it's listed as RESERVED

[Tariq Kurd (tariqkurd-repo)]

Alexander Richardson (Alexander Richardson (@arichardson)) Tariq Kurd (Tariq Kurd (@tariqkurd-repo)) Should the CHERI memory instructions all have type rs1_n0 as it's listed as RESERVED

that is a very good queston and a problematic one - CHERI states that all load/stores are reserved if rs1=x0 as there's always a fault so we should really replace all load/stores with rs1_n0 which we can't easily do so we need a strategy.

[robinali-codasip]

Alexander Richardson (Alexander Richardson (Alexander Richardson (@arichardson))) Tariq Kurd (Tariq Kurd (Tariq Kurd (@tariqkurd-repo))) Should the CHERI memory instructions all have type rs1_n0 as it's listed as RESERVED

that is a very good queston and a problematic one - CHERI states that all load/stores are reserved if rs1=x0 as there's always a fault so we should really replace all load/stores with rs1_n0 which we can't easily do so we need a strategy.

Its interesting because presumably for other load/stores, the behaviour reverts in integral pointer mode but for ly and sy it remains reserved.

[Tariq Kurd (tariqkurd-repo)]

Alexander Richardson (Alexander Richardson (Alexander Richardson (Alexander Richardson (@arichardson)))) Tariq Kurd (Tariq Kurd (Tariq Kurd (Tariq Kurd (@tariqkurd-repo)))) Should the CHERI memory instructions all have type rs1_n0 as it's listed as RESERVED

that is a very good queston and a problematic one - CHERI states that all load/stores are reserved if rs1=x0 as there's always a fault so we should really replace all load/stores with rs1_n0 which we can't easily do so we need a strategy.

Its interesting because presumably for other load/stores, the behaviour reverts in integral pointer mode but for ly and sy it remains reserved.

that does sound inconsistent.....

[Alexander Richardson (arichardson)]

Alexander Richardson (Alexander Richardson (Alexander Richardson (Alexander Richardson (Alexander Richardson (@arichardson))))) Tariq Kurd (Tariq Kurd (Tariq Kurd (Tariq Kurd (Tariq Kurd (@tariqkurd-repo))))) Should the CHERI memory instructions all have type rs1_n0 as it's listed as RESERVED

that is a very good queston and a problematic one - CHERI states that all load/stores are reserved if rs1=x0 as there's always a fault so we should really replace all load/stores with rs1_n0 which we can't easily do so we need a strategy.

Its interesting because presumably for other load/stores, the behaviour reverts in integral pointer mode but for ly and sy it remains reserved.

that does sound inconsistent.....

That was just unclear wording in the spec text, the behaviour has always applied to every load/store only in capability mode.