Visual pre-RTL bottleneck profiler for pccx NPU: Rust/Tauri GUI, UVM co-simulation, trace reports, and LLM-assisted testbench generation.
visualization rust asic fpga profiler verification performance-analysis systemverilog uvm tauri npu edge-ai bottleneck-analysis pre-rtl llm-driven-testbench
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Updated
May 1, 2026 - TypeScript