Skip to content

fix(ram): make verilog write behavior match simulator #817

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
092vk merged 3 commits into from
Feb 24, 2026
Merged

fix(ram): make verilog write behavior match simulator #817

Show file tree
Hide file tree
Changes from 2 commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
8d8a687
fix(ram): make verilog write behavior match simulator
aindree-2005 Jan 17, 2026
230d187
Merge branch 'main' into ram
092vk Feb 23, 2026
7c565b3
Merge branch 'main' into ram
092vk Feb 24, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion src/simulator/src/sequential/RAM.js
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -329,7 +329,7 @@ export default class RAM extends CircuitElement {
assign dout = mem[addr];
always @ (*) begin
if (!we)
if (we)
mem[addr] = din;
end
endmodule
Expand Down
2 changes: 1 addition & 1 deletion v1/src/simulator/src/sequential/RAM.js
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -329,7 +329,7 @@ export default class RAM extends CircuitElement {
assign dout = mem[addr];
always @ (*) begin
if (!we)
if (we)
mem[addr] = din;
end
endmodule
Expand Down
Loading