fix(ram): make verilog write behavior match simulator#817
fix(ram): make verilog write behavior match simulator#817092vk merged 3 commits intoCircuitVerse:mainfrom
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WalkthroughThe embedded Verilog in src/simulator/src/sequential/RAM.js had its write condition inverted: the memory write statement 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
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> [!CAUTION]
Some comments are outside the diff and can’t be posted inline due to platform limitations.
⚠️ Outside diff range comments (1)src/simulator/src/sequential/RAM.js (1)
316-337:⚠️ Potential issue | 🟠 Major
rstport is declared but has no implementation — a remaining gap from issue#816.The linked issue explicitly requires that RESET behavior in the exported Verilog match the simulator. The simulator's
resolve()(Lines 171–173) clears all memory whenreset.value == 1, but the Verilog module declaresrstas an input and never uses it. The same applies todmp.The
always @(*)block should handle the reset case. A minimal fix would look like:🛠️ Proposed fix to add rst support
always @ (*) begin + if (rst) begin + integer i; + for (i = 0; i < 2**ADDR; i = i + 1) + mem[i] = 0; + end else if (we) mem[addr] = din; endNote: resetting the entire array inside a combinational block is still non-idiomatic (synthesis tools may warn), but it would keep the simulation semantics consistent. The pre-existing comment at Lines 314–315 already acknowledges the clock-less design is unusual.
Would you like me to open a new issue or draft a more complete Verilog implementation (including reset and a note on
dmp) to fully close#816?🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed. In `@src/simulator/src/sequential/RAM.js` around lines 316 - 337, The Verilog emitted by RAM.moduleVerilog() declares rst and dmp but never uses them, so update moduleVerilog() to implement the simulator's reset semantics (matching resolve() which clears mem when reset.value == 1): in the always @(*) block add a branch that when rst is asserted it clears the entire mem (set mem[...] = 0 for all addresses) and otherwise performs the existing write-on-we behavior; also decide how to handle dmp (either mirror rst or implement intended dump behavior) and reference rst and dmp in the always block so both ports are used. Ensure changes are made inside the module string returned by moduleVerilog() so emitted Verilog matches the simulator's reset behavior.
🤖 Prompt for all review comments with AI agents
Verify each finding against the current code and only fix it if needed.
Outside diff comments:
In `@src/simulator/src/sequential/RAM.js`:
- Around line 316-337: The Verilog emitted by RAM.moduleVerilog() declares rst
and dmp but never uses them, so update moduleVerilog() to implement the
simulator's reset semantics (matching resolve() which clears mem when
reset.value == 1): in the always @(*) block add a branch that when rst is
asserted it clears the entire mem (set mem[...] = 0 for all addresses) and
otherwise performs the existing write-on-we behavior; also decide how to handle
dmp (either mirror rst or implement intended dump behavior) and reference rst
and dmp in the always block so both ports are used. Ensure changes are made
inside the module string returned by moduleVerilog() so emitted Verilog matches
the simulator's reset behavior.
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📒 Files selected for processing (2)
src/simulator/src/sequential/RAM.jsv1/src/simulator/src/sequential/RAM.js
🚧 Files skipped from review as they are similar to previous changes (1)
- v1/src/simulator/src/sequential/RAM.js
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@aindree-2005 Thanks for the PR, its merged now |
2 participants
Fixes #816
Describe the changes you have made in this PR -
This PR fixes a WRITE-enable polarity mismatch between the RAM simulator and exported Verilog.
Screenshots of the UI changes (If any) -
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