Skip to content

Single-bit std_logic to a slice (ghdl) #28

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
darsor merged 2 commits into from
Nov 4, 2025
Merged

Single-bit std_logic to a slice (ghdl) #28

Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
c085d77
peakrdl-regblock-vhdl used (0 => value) when assigning single-bit std…
davekeeshan Nov 1, 2025
fc5ea7b
Fix to use to_std_logic_vector instead of =>
davekeeshan Nov 4, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions src/peakrdl_regblock_vhdl/readback/generators.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -248,7 +248,7 @@ def process_buffered_reg_with_bypass(self, node: RegNode, regwidth: int, accessw

if field.width == 1:
# convert from std_logic to std_logic_vector
value = f"(0 => {value})"
value = f"to_std_logic_vector({value})"
self.add_content(f"readback_array({self.current_offset_str})({field.high} downto {field.low}) <= {value} when {rd_strb} else (others => '0');")
bidx = field.high + 1

Expand Down Expand Up @@ -317,7 +317,7 @@ def process_wide_reg(self, node: RegNode, accesswidth: int) -> None:

if field.width == 1:
# convert from std_logic to std_logic_vector
value = f"(0 => {value})"
value = f"to_std_logic_vector({value})"
self.add_content(f"readback_array({self.current_offset_str})({high} downto {low}) <= {value} when {rd_strb} else (others => '0');")

current_bit = field.high + 1
Expand Down