Fix issues when trying to parameterize Verilog modules#945

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piotrva wants to merge 2 commits intoVUnit:masterfrom

piotrva:fix-verilog-case-sensitivity

Commits on Jul 12, 2023

Try both lower-case transformed design unit name as well as original format to fix issue with Verilog being case-sensitive.
Piotr Rzeszut
committed

Commits on Oct 5, 2023

Move case-sensitivity check to get_test_bench (see #945)
piotrva
committed