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Fix issues when trying to parameterize Verilog modules #945

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Fix issues when trying to parameterize Verilog modules #945

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161d370
Try both lower-case transformed design unit name as well as original …
Jul 12, 2023
ea31327
Move case-sensitivity check to get_test_bench (see #945)
piotrva Oct 5, 2023
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5 changes: 4 additions & 1 deletion vunit/test/bench_list.py
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Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,10 @@ def _add_test_bench(self, test_bench):
self._libraries[test_bench.library_name][test_bench.name] = test_bench

def get_test_bench(self, library_name, name):
return self._libraries[library_name][name]
try:
return self._libraries[library_name][name]
except KeyError:
return self._libraries[library_name][name.lower()]

def get_test_benches_in_library(self, library_name):
return list(self._libraries.get(library_name, {}).values())
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2 changes: 0 additions & 2 deletions vunit/ui/library.py
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Expand Up @@ -486,8 +486,6 @@ def test_bench(self, name):
:returns: A :class:`.TestBench` object
:raises: KeyError
"""
name = name.lower()

return TestBench(self._test_bench_list.get_test_bench(self._library_name, name), self)

def get_test_benches(self, pattern="*", allow_empty=False):
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