Release Notes for GHRD for Agilex 5 FPGA E-Series 25.3
Release Information:
Quartus Version: 25.3 Build 109 09/24/2025 SC Pro Edition
Tag: QPDS25.3_REL_GSRD_PR
Build: socfpga_ghrd_a5e_base/25.3/1964
New Features and Enhancements
-
New baseline design
- Refer to README.md for details.
- Highlights:
- This design restructures legacy-baseline design to improve ease of use.
- The core and hps subsystem are clearly separated with minimal interconnect logics.
- The yocto build targets for sd and qspi images are also included in the Makefile. This will provide a design specific software.
-
HPS Baseline System Example Design for Agilex 5 FPGA E-Series 013B Development Kit
Issues Resolved
- Fixed incorrect weak pull up assignment. Applicable for HPS IO pin will be assigned with 20kOhm pullup resistor.
- Disable EMIF REQ and WEQ calibration in EMIF IP to reduce boot time.
Latest Known Issues
- No support for HPS NAND board due to ECC issue.
- Non-optimal soft PHY Clock Divider for a5ed065es-premium-devkit-oobe/baseline and a5ed013-devkit-oobe/legacy-baseline designs. Setting div4 will cause SD modes that require more than 50MHz to fail. This will be improved in next release.
For 25.3, user can either change the divider to div1 in platform designer or edit this two lines with value 1.
https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/QPDS25.3_REL_GSRD_PR/a5ed065es-premium-devkit-oobe/baseline/ip/hps_comp/agilex_hps.ip#L9503
https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/QPDS25.3_REL_GSRD_PR/a5ed013-devkit-oobe/legacy-baseline/ip/hps_subsys/agilex_hps.ip#L7956