GHRD for Agilex 5 FPGA E-Series 25.3 Release

Release Notes for GHRD for Agilex 5 FPGA E-Series 25.3

Release Information:

Quartus Version: 25.3 Build 109 09/24/2025 SC Pro Edition
Tag: QPDS25.3_REL_GSRD_PR
Build: socfpga_ghrd_a5e_base/25.3/1964

New Features and Enhancements

• New baseline design

  • Refer to README.md for details.
  • Highlights:
    • This design restructures legacy-baseline design to improve ease of use.
    • The core and hps subsystem are clearly separated with minimal interconnect logics.
    • The yocto build targets for sd and qspi images are also included in the Makefile. This will provide a design specific software.

• HPS Baseline System Example Design for Agilex 5 FPGA E-Series 013B Development Kit

Issues Resolved

• Fixed incorrect weak pull up assignment. Applicable for HPS IO pin will be assigned with 20kOhm pullup resistor.
• Disable EMIF REQ and WEQ calibration in EMIF IP to reduce boot time.

Latest Known Issues

• No support for HPS NAND board due to ECC issue.
• Non-optimal soft PHY Clock Divider for a5ed065es-premium-devkit-oobe/baseline and a5ed013-devkit-oobe/legacy-baseline designs. Setting div4 will cause SD modes that require more than 50MHz to fail. This will be improved in next release.
  For 25.3, user can either change the divider to div1 in platform designer or edit this two lines with value 1.
  https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/QPDS25.3_REL_GSRD_PR/a5ed065es-premium-devkit-oobe/baseline/ip/hps_comp/agilex_hps.ip#L9503
  https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/QPDS25.3_REL_GSRD_PR/a5ed013-devkit-oobe/legacy-baseline/ip/hps_subsys/agilex_hps.ip#L7956

GHRD for Agilex 5 FPGA E-Series 25.1.1 Release

Release Notes for GHRD for Agilex 5 FPGA E-Series 25.1.1

Release Information:

Quartus Version: 25.1.1 Build 125 07/31/2025 SC Pro Edition
Tag: QPDS25.1.1_REL_GSRD_PR
Build: socfpga_ghrd_a5e_base/25.1.1/1354

New Features and Enhancements

• EMIF ECC is enabled for all designs.
• Premium Development Kit with Out of Box Experience (OOBE) daughter card designs support USB3.1.

Issues Resolved

• Corrected usb31_phy_refclk_p_clk and usb31_phy_refclk_p_clk(n) pin for Agilex 5 FPGA E-Series 065B Modular Development Kit.
• Fixed wrong value in agilex_hps.ip file, that creates wrong handoff to powerdown the SDMMC controller.

Latest Known Issues

• Remove support for HPS NAND board due to ECC issue.

GHRD for Agilex 5 FPGA E-Series 25.1 Release

Release Notes for GHRD for Agilex 5 FPGA E-Series 25.1

Release Information:

Quartus Version: 25.1.0 Build 129 03/26/2025 SC Pro Edition
Quartus Patches: None
Tag: QPDS25.1_REL_GSRD_PR
Build: socfpga_ghrd_a5e_base/25.1/621

New Features and Enhancements

GHRD for Agilex 5 FPGA E-Series 25.1 includes the following new features and enhancements:

• For previous releases, all GHRD designs are hosted in altera-opensource/ghrd-socfpga. Starting from 25.1, the Agilex 5 E-series FPGA GHRD designs will be hosted in this repo.
• Repository Restructure. For previous releases, users need to generate the GHRD designs manually. From 25.1 all design files for supported Agilex 5 GHRD are checked in. Designs are grouped according to the Development Kit and Daughter Cards in individual folders. After cloning the repository, users can navigate to the desired folder and open the design directly with Quartus. Refer to README.md for the supported designs and details.
• Timing violation and pin assignment warnings are promoted to error to ensure that the design sof file can be generated successfully.
  Re-factored Makefile to build the designs for the new repository structure. Refer to README.md for the detailed instructions.
  Prebuild binaries and design files as release assets in altera-fpga. They can be downloaded directly with Quartus. Refer accessing-downloaded-design-examples for details.

Latest Known Issues

None

Issues Resolved

None