A test PR for #140694 while waiting for #149110 to complete #149824
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✅ With the latest revision this PR passed the C/C++ code formatter. |
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Rebased on to main to clear regression of ptradd-sdag-optimizations.ll. |
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Add to the VOP patterns to recognise when or/xor/and are modifying only the sign bit and replace with the appropriate srcmod.
64-bit wide instructions Make use of s_or_b64/s_and_b64/s_xor_b64 for v2i32. Legalising these causes a number of test regressions, so extra work in the combiner and Tablegen patterns was necessary. - Use custom for v2i32 rotr instead of additional patterns. Modify PerformOrCombine() to remove some identity or operations - Fix rotr regression by adding lowerRotr() on the legalizer codepath. - Add test case to rotr.ll - Extend performFNEGCombine() for the SELECT case. - Modify performSelectCombine() and foldFreeOpFromSelect to prevent the performFNEGCombine() changes from being unwound. - Add cases to or.ll and xor.ll to demonstrate the generation of the s_or_64 and s_xor_64 instructions for the v2i32 cases. Previously this was inhibited by "-amdgpu-scalarize-global-loads=false". - Fix shl/srl64_reduce regression by performing the scalarisation previously performewd by the vector legaliser in the combiner.
…aken place for tens of other tests.
This prevents any regressions in feng-modifier-casting.ll.
is made legal for or/xor/and. Complete fix of v2i32 in VOP SrcMod placement.
Factor shift reducing combine logic into one function as it was applied in all three shift combine functions.
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#149110
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#140694