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merged 3 commits into from
Aug 12, 2025

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dansalvato
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@dansalvato dansalvato commented Aug 7, 2025

M68k's SETCC instruction (scc) distinctly fills the destination byte with all 1s. If boolean contents are set to ZeroOrOneBooleanContent, LLVM can mistakenly think the destination holds 0x01 instead of 0xff and emit broken code as a result. This change corrects the boolean content type to ZeroOrNegativeOneBooleanContent.

For example, this IR:

define dso_local signext range(i8 0, 2) i8 @testBool(i32 noundef %a) local_unnamed_addr #0 {
entry:
  %cmp = icmp eq i32 %a, 4660
  %. = zext i1 %cmp to i8
  ret i8 %.
}

would previously build as:

testBool:                               ; @testBool
	cmpi.l	#4660, (4,%sp)
	seq	%d0
	and.l	#255, %d0
	rts

Notice the zext is erroneously not clearing the low bits, and thus the register returns with 255 instead of 1. This patch fixes the issue:

testBool:                               ; @testBool
	cmpi.l	#4660, (4,%sp)
	seq	%d0
	and.l	#1, %d0
	rts

Most of the tests containing scc suffered from the same value error as described above, so those tests have been updated to match the new output (which also logically corrects them).

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llvmbot commented Aug 7, 2025

@llvm/pr-subscribers-backend-m68k

Author: Dan Salvato (dansalvato)

Changes

M68k's SETCC instruction (scc) distinctly fills the destination byte with all 1s. If boolean contents are set to ZeroOrOneBooleanContent, LLVM can mistakenly think the destination holds 0x01 instead of 0xff and emit broken code as a result. This change corrects the boolean content type to ZeroOrNegativeOneBooleanContent.

For example, this IR:

define dso_local signext range(i8 0, 2) i8 @<!-- -->testBool(i32 noundef %a) local_unnamed_addr #<!-- -->0 {
entry:
  %cmp = icmp eq i32 %a, 4660
  %. = zext i1 %cmp to i8
  ret i8 %.
}

would previously build as:

testBool:                               ; @<!-- -->testBool
	cmpi.l	#<!-- -->4660, (4,%sp)
	seq	%d0
	and.l	#<!-- -->255, %d0
	rts

Notice the zext is erroneously not clearing the low bits, and thus the register returns with 255 instead of 1. This patch fixes the issue:

testBool:                               ; @<!-- -->testBool
	cmpi.l	#<!-- -->4660, (4,%sp)
	seq	%d0
	and.l	#<!-- -->1, %d0
	rts

Full diff: https://github.com/llvm/llvm-project/pull/152572.diff

1 Files Affected:

  • (modified) llvm/lib/Target/M68k/M68kISelLowering.cpp (+1-1)
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index 594ea9f48c201..c6a20e211df7d 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -51,7 +51,7 @@ M68kTargetLowering::M68kTargetLowering(const M68kTargetMachine &TM,
 
   MVT PtrVT = MVT::i32;
 
-  setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanContents(ZeroOrNegativeOneBooleanContent);
 
   auto *RegInfo = Subtarget.getRegisterInfo();
   setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());

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Requesting review from @mshockwave

@dansalvato dansalvato force-pushed the m68k-boolean-contents branch from 1459e58 to 3565d7a Compare August 7, 2025 21:51
@nikic nikic requested a review from mshockwave August 8, 2025 09:55
M68k's SETCC instruction (`scc`) distinctly fills the destination byte
with all 1s. If boolean contents are set to `ZeroOrOneBooleanContent`,
LLVM can mistakenly think the destination holds `0x01` instead of `0xff`
and emit broken code as a result. This change corrects the boolean
content type to `ZeroOrNegativeOneBooleanContent`.
@dansalvato dansalvato force-pushed the m68k-boolean-contents branch from 3565d7a to 65ecc9d Compare August 8, 2025 18:02
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LGTM, nice catch.
M68k's SysV ABI didn't really specify the boolean values but I'm fine using SETCC's representation as that's how we lower in most cases

@dansalvato
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Thank you, please feel free to merge on my behalf since I don't have write access to the repo.

@mshockwave mshockwave merged commit b09b05a into llvm:main Aug 12, 2025
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@dansalvato dansalvato deleted the m68k-boolean-contents branch August 12, 2025 15:49
dansalvato added a commit to dansalvato/llvm-project that referenced this pull request Aug 12, 2025
M68k's SETCC instruction (`scc`) distinctly fills the destination byte
with all 1s. If boolean contents are set to `ZeroOrOneBooleanContent`,
LLVM can mistakenly think the destination holds `0x01` instead of `0xff`
and emit broken code as a result. This change corrects the boolean
content type to `ZeroOrNegativeOneBooleanContent`.

For example, this IR:

```llvm
define dso_local signext range(i8 0, 2) i8 @testBool(i32 noundef %a) local_unnamed_addr #0 {
entry:
  %cmp = icmp eq i32 %a, 4660
  %. = zext i1 %cmp to i8
  ret i8 %.
}
```

would previously build as:

```asm
testBool:                               ; @testBool
	cmpi.l	llvm#4660, (4,%sp)
	seq	%d0
	and.l	llvm#255, %d0
	rts
```

Notice the `zext` is erroneously not clearing the low bits, and thus the
register returns with 255 instead of 1. This patch fixes the issue:

```asm
testBool:                               ; @testBool
	cmpi.l	llvm#4660, (4,%sp)
	seq	%d0
	and.l	llvm#1, %d0
	rts
```

Most of the tests containing `scc` suffered from the same value error as
described above, so those tests have been updated to match the new
output (which also logically corrects them).
dansalvato added a commit to dansalvato/llvm-project that referenced this pull request Aug 12, 2025
M68k's SETCC instruction (`scc`) distinctly fills the destination byte
with all 1s. If boolean contents are set to `ZeroOrOneBooleanContent`,
LLVM can mistakenly think the destination holds `0x01` instead of `0xff`
and emit broken code as a result. This change corrects the boolean
content type to `ZeroOrNegativeOneBooleanContent`.

For example, this IR:

```llvm
define dso_local signext range(i8 0, 2) i8 @testBool(i32 noundef %a) local_unnamed_addr #0 {
entry:
  %cmp = icmp eq i32 %a, 4660
  %. = zext i1 %cmp to i8
  ret i8 %.
}
```

would previously build as:

```asm
testBool:                               ; @testBool
	cmpi.l	llvm#4660, (4,%sp)
	seq	%d0
	and.l	llvm#255, %d0
	rts
```

Notice the `zext` is erroneously not clearing the low bits, and thus the
register returns with 255 instead of 1. This patch fixes the issue:

```asm
testBool:                               ; @testBool
	cmpi.l	llvm#4660, (4,%sp)
	seq	%d0
	and.l	llvm#1, %d0
	rts
```

Most of the tests containing `scc` suffered from the same value error as
described above, so those tests have been updated to match the new
output (which also logically corrects them).
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3 participants