Skip to content

Conversation

arsenm
Copy link
Contributor

@arsenm arsenm commented Sep 2, 2025

This should be trying to use the _gfx9 variants of DS pseudos,
not the base form with m0 uses.

Copy link
Contributor Author

arsenm commented Sep 2, 2025

: DS_1A1D_NORET_mc<opName, rc> {
let has_m0_read = 0 in {
let True16Predicate = UseRealTrue16Insts in {
def "_t16" : DS_1A1D_NORET<opName#"_t16", VGPR_16>, True16D16Table<NAME#"_D16_HI", NAME>;
def "_t16" : DS_1A1D_NORET<opName#"_t16", VGPR_16>,
True16D16Table<NAME#"_D16_HI", NAME#"_gfx9">;
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Why gfx9, it does not have t16?

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Oh, I see, we do not define gfx11/gfx12 pseudos.

Copy link
Collaborator

@rampitec rampitec left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

: DS_1A1D_NORET_mc<opName, rc> {
let has_m0_read = 0 in {
let True16Predicate = UseRealTrue16Insts in {
def "_t16" : DS_1A1D_NORET<opName#"_t16", VGPR_16>, True16D16Table<NAME#"_D16_HI", NAME>;
def "_t16" : DS_1A1D_NORET<opName#"_t16", VGPR_16>,
True16D16Table<NAME#"_D16_HI", NAME#"_gfx9">;
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Oh, I see, we do not define gfx11/gfx12 pseudos.

@arsenm arsenm changed the base branch from users/arsenm/amdgpu/true16-handle-ds-write-b8-b16 to main September 3, 2025 00:02
This should be trying to use the _gfx9 variants of DS pseudos,
not the base form with m0 uses.
@arsenm arsenm force-pushed the users/arsenm/amdgpu/fix-true16-d16-table-pseudo-entry branch from 849b10b to 21fa4b7 Compare September 3, 2025 00:04
@arsenm arsenm enabled auto-merge (squash) September 3, 2025 00:05
@arsenm arsenm merged commit 681046e into main Sep 3, 2025
9 checks passed
@arsenm arsenm deleted the users/arsenm/amdgpu/fix-true16-d16-table-pseudo-entry branch September 3, 2025 00:45
@llvmbot
Copy link
Member

llvmbot commented Sep 3, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

This should be trying to use the _gfx9 variants of DS pseudos,
not the base form with m0 uses.


Full diff: https://github.com/llvm/llvm-project/pull/156419.diff

1 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/DSInstructions.td (+3-2)
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 2ff9dfe8a7014..e6a07ebe1cafb 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -127,11 +127,12 @@ multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
   }
 }
 
-multiclass DS_1A1D_NORET_t16<string opName, RegisterClass rc = VGPR_32> 
+multiclass DS_1A1D_NORET_t16<string opName, RegisterClass rc = VGPR_32>
 : DS_1A1D_NORET_mc<opName, rc> {
   let has_m0_read = 0 in {
     let True16Predicate = UseRealTrue16Insts in {
-      def "_t16" : DS_1A1D_NORET<opName#"_t16", VGPR_16>, True16D16Table<NAME#"_D16_HI", NAME>;
+      def "_t16" : DS_1A1D_NORET<opName#"_t16", VGPR_16>,
+        True16D16Table<NAME#"_D16_HI", NAME#"_gfx9">;
     }
   }
 }

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants