Add a discrete debug module simulation mode #2274
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hcallahan-lowrisc
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Type:Enhancement
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Draft while I sort out CI breakage, but I don't anticipate huge structural changes from here. |
rswarbrick
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May 30, 2025
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These assertions were a little too strong. While in practice the halt and exception vector addresses would likely be within the range of the debug_module, this is not mandated by the specification. We actually do this is the current testbench configuration. The halt and exception vectors are parameterized to `BOOT_ADDR and `BOOT_ADDR + 0x4 respectively, and the riscv-dv generated test binaries insert jump handlers at those locations that target the .debug_rom and .debug_exception sections somewhere else in the monolithic test binary. The assertions only worked because the current parameterizations for Debug Module addresses put the debug module right at the BOOT_ADDR parameter, which doesn't really make much sense. .DmBaseAddr (32'h`BOOT_ADDR) .DmAddrMask (32'h0000_0007 ) MTVEC is reset to `BOOT_ADDR, so this memory region would normally be used for the mmode trap handler vector table. Signed-off-by: Harry Callahan <[email protected]>
In the future we probably want use Fusesoc to generate the filelist, which can be dropped in place of the ibex_dv.f file now that it only contains file includes. +define+BOOT_ADDR will also be removed, to be incorporated into the python scripting in a follow up commit. Signed-off-by: Harry Callahan <[email protected]>
In particular, this makes use of the new method processor_t::set_debug_module_range(reg_t start_debug_val, reg_t end_debug_val) Signed-off-by: Harry Callahan <[email protected]>
When passing +is_discrete_debug_module to 'sim_opts' in the riscv-dv testlist (dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml), this now results in the test being compiled and loaded into the simulation memory models in a way that mimics a discrete debug module mapped away from the main processor memory. Up to this point, the riscv-dv binaries generate debug rom sections which are simply placed within a single monolithic code section. This requires a bit of machinery to achieve: - A new linker script to compile our test software for this layout (riscv_dv_extension/link.ld - Test binaries output into multiple binaries which are loaded seperately to initialize the sparse memory space. Two regions are supported, 'main' and 'dm'. - Initialize more testbench parameters via CLI args. This allows their values to be chosen dynamically in the future and to be test-dependent. For now, the various address / mask parameters are still set to fixed values for all tests. One slightly unclean implementation detail is that the cosimulation model's memory is loaded via binary .bin files, while the simulator's memory model is loaded via verilog .vmem memory files. Ideally we would use .vmem files for both, but the interface to the cosimulation model via DPI only implements byte-writes, so loading a raw binary file is more convenient for that interface. Signed-off-by: Harry Callahan <[email protected]>
This also matches an equivalent change in spike, which still configures this address via a preprocessor macro. Signed-off-by: Harry Callahan <[email protected]>
Signed-off-by: Harry Callahan <[email protected]>
Signed-off-by: Harry Callahan <[email protected]>
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Note. do not merge without coordination. Due to the way we handle the external spike dependency, lowRISC/riscv-isa-sim#26 will need to be merged in coordination with this PR to avoid CI breakage.
This PR adds a mechanism for testing ibex in a memory system that provisions code in a way to mimic the presence of a discrete external debug module.
This PR just adds the machinery to implement this. Follow up merges will add new tests that make use of it.
Desc.
When passing +is_discrete_debug_module to 'sim_opts' in the riscv-dv testlist
(dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml), this now results in the test
being compiled and loaded into the simulation memory models in a way that mimics
a discrete debug module mapped away from the main processor memory. Up to this
point, the riscv-dv binaries generate debug rom sections which are simply placed
within a single monolithic code section.
This requires a bit of machinery to achieve:
(
riscv_dv_extension/link.ld)initialize the sparse memory space. Two regions are supported, 'main' and 'dm'.
to be chosen dynamically in the future and to be test-dependent. For now, the
various address / mask parameters are still set to fixed values for all tests.
One slightly unclean implementation detail is that the cosimulation model's
memory is loaded via binary .bin files, while the simulator's memory model is
loaded via verilog .vmem memory files. Ideally we would use .vmem files for
both, but the interface to the cosimulation model via DPI only implements
byte-writes, so loading a raw binary file is more convenient for that interface.
TODO
This could probably do with some standalone documentation, as there are still some
assumptions that glue the different steps together (.e.g .section names in the linker script).
However, this is broadly true for the entire DV architecture.