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@ThinkOpenly ThinkOpenly requested a review from dhower-qc as a code owner May 1, 2025 23:35
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@AFOliveira AFOliveira left a comment

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I don't think the pseudoinstructions to should be the assembly representation. Likely, the pseudoinstructions need a re-structure that allows that represenation, but for now I don't think we should place that information in a field that is not meant to accomodate it

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Other than the two whitespaces, I think all looks good!

Also fix a few places where integer registers were still being referred
to as `r` instead of `x`.

Also, fix a few operand specifications
`csrrci` and `csrrsi` take "xd, csr, imm" not "rd, imm, rs1").
"zero" is not a constant in IDL.

Also, add a comment to "fence" pseudoinstruction, since it maps
to "fence" instruction with "iorw,iorw" operands.
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LGTM!

@ThinkOpenly ThinkOpenly added this pull request to the merge queue May 6, 2025
Merged via the queue into riscv-software-src:main with commit 3dfd0fe May 6, 2025
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@ThinkOpenly ThinkOpenly deleted the pseudos branch May 6, 2025 19:21
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3 participants