drivers: flash: spi_nor: Set 4-byte addr mode via Bank Addr Reg #77845
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talih0
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I can fix this compliance warning but it will make the registers misaligned :S
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drivers/flash/spi_nor.h
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Don't name the command. This is Infineon specific name for the command that itself has no name in JEDEC specification, that is not SPI_NOR_CMD name, that is Infineon SPI_NOR_CMD name.
I know that we have been naming things here and there, but I think we start to have a problem here where we can start collision of naming things with identifiers provided by vendors doc.
The JEDEC spec does not name the command only gives info that 0x16 is read and 0x17 is write, and that lower 7 bits of register translate, under condition, to as 128Mbit "segment". The definition here states "Bank", which is something Infineon doc defines, not JEDEC, and may additionally collide with defs from other vendors for the same command, in naming.
drivers/flash/spi_nor.c
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Comment here on JEDEC 216F description of Enter 4-Byte Addressing and just use hardcoded 0x17 with explanation in comment.
Some flash devices enable entering the 4-byte address mode by setting BIT(7) in a special register via a write instruction 0x17. The support for this method is indicated in BIT(3) of Enter 4-Byte Addressing byte in 16th DWORD of the JEDEC Basic Flash Parameter Table. Infineon's S25FL512S is an example flash device with this feature. Signed-off-by: Andriy Gelman <[email protected]>
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@de-nordic, I updated the comments and removed the changes in the spi_nor.h. Let me know if the updated version is ok. |
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@de-nordic ping please |
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Some flash devices enable entering the 4-byte address mode by setting BIT(7) in the Bank Address register (0x17). The support for this method is indicated in BIT(3) of Enter 4-Byte Addressing byte in 16th DWORD of the JEDEC Basic Flash Parameter Table.
Infineon's S25FL512S is an example flash device with this feature.