boards: beaglev_fire: improve docs, fix uart, expand RAM

[AlexCharlton]

This PR makes three small changes, all aimed at improving BeagleV-Fire support.

Update documentation

Aside from some minor clarifications, a "Flashing" section was added, since the steps to flash the Fire in a way that's compatible with the Microchip-provided Hart Software Services (HSS) is not readily accomplished with west/make flash. An example of west scripts that are able to flash the Fire can be seen here, but I doubt this ought to live in Zephyr proper.

Change selected UART

In 166b9bf#diff-01f5d360c1043dce50bf74fbb1cc056d2049160741e483f843c19d081c065252R18 the selected UART was changed from uart0 to uart1, presumably to mirror the changes made to the other PolarFire boards. While this makes sense to do for the Icicle kit, from looking at the Fire's schematics, I don't believe any of the UARTs other than uart0 is hooked up to anything.

Expand available RAM

sram0 is a relatively small region of RAM, meant to be used by the HSS (see Linux device tree). I see no reason why sram1 shouldn't occupy the remaining ~2GB present on the Fire. I'm a Zephyr newbie, however, so I'm not sure if there are any reasons why you would want to limit the RAM defined.

[github-actions]

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[AlexCharlton]

Noting that these doc fixes overlap with #79511. My doc additions do cover the flashing instructions which were noted as missing in that PR.

[con-pax]

Hey @AlexCharlton, thanks for the PR! It all looks good to me. I will test it on the Beagle today.
Cheers

[AlexCharlton]

Thanks @con-pax! I should have noted that I tested this out on my Fire, and it Works For Me 🙂

[con-pax]

LGTM

6.406446] >> *** Booting Zephyr OS build v4.0.0-rc1-79-g464e68645d7f ***
Hello World! beaglev_fire/polarfire/e51

464e68645d7 (HEAD -> main, origin/main, origin/HEAD) boards: beaglev_fire: expand RAM

pc             0x80000290	0x80000290 <main+24>

[AlexCharlton]

In addition to fixing the board identifiers, I caught a serious issue in my change. I only just found the authoritative docs for PolarFire memory layout. And this clearly shows that address 0x8000_0000 has an upper range of 0xC000_0000 (1GB shy of the 2GB desired).

Instead, we need to use addresses in the 64bit range if we want to span more than 1GB. In particular 0x10_0000_0000 is the correct starting point for cached DDR.

To accomplish this, I defined a new node in the device tree for this memory region,beaglev.ddr_cached_high. Unlike previously, I couldn't reuse the soc node because we needed to set the #address-cells to be 2, and doing so would have affected other nodes under soc.

Here you can see hello world booting into the updated address range:

[7.295341] Attempting to select eMMC ... Passed
[8.74206] Preparing to copy from MMC to DDR ...
[8.79596] GPT_PartitionIdToLBAOffset() failed - using offset 0
[8.86540] Attempting to read image header (1632 bytes) ...    
[8.92876] Copying 15456 bytes to 0x103fc00000                      <--------------
[8.98310] MMC: Boot Image registered ...
[8.103127] Boot image passed CRC
[8.107468] Boot image set name: "PolarFire-SoC-HSS::ZephyrTESTImage"
*** Booting Zephyr OS build v3.7.0-4263-ge40fa8914fad ***
Hello World! beaglev_fire/polarfire/u54

[kartben]

@jadonk we still don't have you properly set up as a maintainer, apparently...

[kartben]

rebased to re-trigger incomplete CI

[github-actions]

Hi @AlexCharlton!
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Thank you for your valuable input, and we look forward to seeing more of your contributions in the future! 🪁