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enable ethernet support on the stm32mp135f-dk #96134
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The following west manifest projects have changed revision in this Pull Request:
Additional metadata changed:
⛔ DNM label due to: 1 project with metadata changes and 2 blob changes Note: This message is automatically posted and updated by the Manifest GitHub Action. |
# Zephyr Kernel Configuration | ||
CONFIG_KERNEL_DIRECT_MAP=y |
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Should this really be part of the board _defconfig
?
Doesn't it apply to the series in general ?
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Right, as we use MMU_REGION_FLAT_ENTRY
in https://github.com/zephyrproject-rtos/zephyr/blob/main/soc/st/stm32/stm32mp13x/soc.c we need is at Soc level
# UART console (overrides remote proc console) | ||
CONFIG_UART_CONSOLE=y | ||
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# Enable I2C support |
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# Enable I2C support | |
# Enable I2C support (for mcp23017 GPIO expander) |
Alternatively, could be enabled depending on expander compatible status in .defconfig file.
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GPIO_MCP230XX should select I2C, instead of depending on it. see https://docs.zephyrproject.org/latest/build/kconfig/tips.html#select-recommendations
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@maass-hamburg
Seems we are facing "egg or chicken" dilemma between I2C and GPIO_MCP230XX should I replace depends on I2C
menuconfig GPIO_MCP230XX
bool "MCP230XX I2C-based GPIO chip"
default y
depends on DT_HAS_MICROCHIP_MCP23008_ENABLED || \
DT_HAS_MICROCHIP_MCP23009_ENABLED || \
DT_HAS_MICROCHIP_MCP23016_ENABLED || \
DT_HAS_MICROCHIP_MCP23017_ENABLED || \
DT_HAS_MICROCHIP_MCP23018_ENABLED
- depends on I2C
+ select I2C
select GPIO_MCP23XXX
help
Enable driver for MCP230XX I2C-based GPIO chip.
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yes
&rcc { | ||
clock-frequency = <DT_FREQ_M(1000)>; | ||
clocks = <&pll>; | ||
clocks = <&pll &pll4>; |
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clocks
here is the main clock tree input. Only one entry is supported.
FYI, it'll have to be rebased on top of #96095 |
reset-gpios: | ||
type: phandle-array | ||
description: | | ||
This reset gpio can be used for PHY with hardware reset. |
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the ethernet-phy driver is meant to be generic and only implement features, that are defined in the ethernet standard IEEE 802.3. It doesn't specify a reset pin, only the register, which should be enought. If you want a reset pin, you have to create a specific phy driver.
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I have created a LAN8742 inspired from ethernet_phy
drivers/ethernet/eth_stm32_hal_v2.c
Outdated
(clock_control_subsys_t)&cfg->pclken_tx); | ||
ret |= clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), | ||
(clock_control_subsys_t)&cfg->pclken_rx); | ||
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32mp13_ethernet) |
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Can't you check DT_INST_CLOCKS_HAS_NAME(0, mac_clk)
instead ?
drivers/ethernet/eth_stm32_hal_v2.c
Outdated
struct eth_stm32_hal_dev_data *dev_data = dev->data; | ||
const struct eth_stm32_hal_dev_cfg *cfg = dev->config; | ||
ETH_HandleTypeDef *heth = &dev_data->heth; | ||
uint8_t *desc_uncached_addr; |
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uint8_t *desc_uncached_addr; | |
__maybe_unused uint8_t *desc_uncached_addr; |
drivers/ethernet/eth_stm32_hal_v2.c
Outdated
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32mp13_ethernet) | ||
/* APO test : TBD */ | ||
heth->Init.ClockSelection = cfg->ClockSelection; |
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Ideally please use clock_control_configure()
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I would prefer not use it. The concerning register is a SYSCFG register that is updated by HAL_ETH_Init()
function.
If I set it before calling HAL_ETH_Init()
it will overwritte it
Else if set it after HAL_ETH_Init()
it could generate side effect.
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To be able to run Zperf we need #96575 |
Add new flags to allow to select normal and strong ordered attributes for non-cacheable memory. This is needed for armV7 to be able to configure all non cacheable memories with another attribute than "device" attribute. Signed-off-by: Arnaud Pouliquen <[email protected]>
Selecting MT_DEVICE for non cache-able memory does no work in all use cases. For instance for net samples a non-cacheable memory can be used for descriptors and buffers exchanged between the lib and the hardware. In such context, the net lib can perform some non word aligned memory this lead to an alignment data abort if the attribute is MT_DEVICE. Memories attribute should be MT_NORMAL, allowing non aligned transfer Signed-off-by: Arnaud Pouliquen <[email protected]>arch: arm: mmu: allow selecting memory type for non-cacheable memory
New hal_stm32 revision contains pincontrol for the etherent support. Signed-off-by: Arnaud Pouliquen <[email protected]>
Introduce stm32mp13 bindings to support the ethernet peripherals. The "memory-regions" property is used to reference non cacheable memory for the ETH DMA. The "st,ext-phyclk" property aligned Linux binding is used to specify the PHY clock for RMII. Signed-off-by: Arnaud Pouliquen <[email protected]>
Add basic support of the LAN8742 RMII phy. The driver is inspired from the phy_mii generic driver, with the support of a GPIO reset. Signed-off-by: Arnaud Pouliquen <[email protected]>
The GPIO_MCP230XX config currently depends on the I2C config. This means that the board/SoC must enable the I2C config to support MCP23xxx devices. Inverting this dependency allows declaring GPIO_MCP230XX directly in the board/SoC defconfig without explicitly enabling I2C. Signed-off-by: Arnaud Pouliquen <[email protected]> Suggested-by Fin Maaß <[email protected]>
Enable dynamic configuration of region mapping with a 1:1 virtual-to-physical address mapping. This configuration is aligned with the static declaration of the MMU table using MMU_REGION_FLAT_ENTRY macro. Signed-off-by: Arnaud Pouliquen <[email protected]>
Add the Ethernet 0 MAC and MDIO nodes in the device tree. Signed-off-by: Arnaud Pouliquen <[email protected]> Signed-off-by: Arif Balik <[email protected]>
The typedef ETH_TxPacketConfigTypeDef is used consistently in the driver. However, some instances of ETH_TxPacketConfig have not yet been replaced. On the STM32MP13 series, the ETH_TxPacketConfig typedef is no longer defined. This cleanup ensures compatibility and consistency. Signed-off-by: Arnaud Pouliquen <[email protected]>
Add the support of the stm32mp13 ethernet: - Adapt to HAL API - Add support of a memory region in DT for descriptor and buffers - Add support of PHY with/without crystal 50MHz Signed-off-by: Arnaud Pouliquen <[email protected]> Signed-off-by: Arif Balik <[email protected]>
The STM32MP135F-DK board embeds 2 ethernets. Enable the ethernet1 in RMII mode with associated PHY. Signed-off-by: Arnaud Pouliquen <[email protected]> Signed-off-by: Arif Balik <[email protected]>
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This Pull reuest enable the support of the ethernet 1 instance
Hardware details:
Samples tested:
Known current limitation: