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Enable i2s_codec sample on mcxn5xx_evk #96954

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Enable i2s_codec sample on mcxn5xx_evk #96954

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3919bdb
soc: mcxnx4x: Instantiate MICFIL
VitekST Aug 28, 2025
542bfb4
board: mcx_n5xx: Enable MICFIL and da7212 codec on mcx_n5xx
TomasBarakNXP Oct 3, 2025
89451d2
board: mcx_nx4x: format board.c
TomasBarakNXP Oct 3, 2025
2c9d813
samples: i2s_codec: enable i2s_codec sample for mcx_n5xx_evk
TomasBarakNXP Oct 3, 2025
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14 changes: 12 additions & 2 deletions boards/nxp/mcx_nx4x_evk/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -136,7 +136,7 @@ void board_early_init_hook(void)

CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ);

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I wonder if you can enable them in separate patches? If one of them breaks the system one of them would have a hard time doing a bisection.

Please use 1 commit per a logical change so that code can be easier to be reviewed and also bisection and debugging in the future be easier.

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(micfil))
/* < Set up PLL1 */
const pll_setup_t pll1_Setup = {
.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) |
Expand All @@ -149,7 +149,7 @@ void board_early_init_hook(void)
/* Configure PLL1 to the desired values */
CLOCK_SetPLL1Freq(&pll1_Setup);
/* Set PLL1 CLK0 divider to value 1 */
CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U);
CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 2U);
#endif

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm0))
Expand Down Expand Up @@ -213,6 +213,7 @@ void board_early_init_hook(void)

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
CLOCK_EnableClock(kCLOCK_Gpio0);
CLOCK_EnableClock(kCLOCK_Port0);
#endif

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
Expand Down Expand Up @@ -450,6 +451,15 @@ void board_early_init_hook(void)
CLOCK_EnableClock(kCLOCK_Sai1);
#endif

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(micfil))
CLOCK_SetClkDiv(kCLOCK_DivMicfilFClk, 1U);
CLOCK_AttachClk(kPLL1_CLK0_to_MICFILF);
CLOCK_EnableClock(kCLOCK_Micfil);

PORT0->PCR[16] = 0x00001900;
PORT0->PCR[17] = 0x00001900;
#endif

/* Set SystemCoreClock variable. */
SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
}
6 changes: 6 additions & 0 deletions boards/nxp/mcx_nx4x_evk/mcx_n5xx_evk.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -7,3 +7,9 @@
#include <nxp/nxp_mcxn54x.dtsi>
#include "mcx_nx4x_evk.dtsi"
#include "mcx_n5xx_evk-pinctrl.dtsi"

&micfil {
status = "okay";
pinctrl-0 = <&pinmux_micfil>;
pinctrl-names = "default";
};
26 changes: 25 additions & 1 deletion boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk-pinctrl.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -92,7 +92,8 @@

pinmux_sai1: pinmux_sai1 {
group0 {
pinmux = <SAI1_TX_BCLK_PIO3_16>,
pinmux = <SAI1_MCLK_PIO1_21>,
<SAI1_TX_BCLK_PIO3_16>,
<SAI1_TX_FS_PIO3_17>,
<SAI1_TXD0_PIO3_20>,
<SAI1_RX_FS_PIO3_19>,
Expand All @@ -104,6 +105,18 @@
};
};

pinmux_flexcomm2_i2c: pinmux_flexcomm2_i2c {
group0 {
pinmux = <FC2_P0_PIO4_0>,
<FC2_P1_PIO4_1>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
bias-pull-up;
drive-open-drain;
};
};

pinmux_enet_qos: pinmux_enet_qos {
mdio_group {
pinmux = <ENET0_MDC_PIO1_20>,
Expand Down Expand Up @@ -237,4 +250,15 @@
bias-pull-up;
};
};

pinmux_micfil: pinmux_micfil {
group0 {
pinmux = <PDM0_CLK_PIO0_16>,
<PDM0_DATA0_PIO0_17>,
<PDM0_DATA1_PIO0_18>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
};
};
13 changes: 13 additions & 0 deletions boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk_cpu0.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -100,6 +100,19 @@

&flexcomm2_lpi2c2 {
status = "okay";
pinctrl-0 = <&pinmux_flexcomm2_i2c>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;

audio_codec: da7212@1a {
compatible = "dialog,da7212";
reg = <0x1a>;
clocks = <&syscon MCUX_SAI1_CLK>;
clock-source = "MCLK";
clock-names = "mclk";
};
};

/*
Expand Down
73 changes: 73 additions & 0 deletions dts/arm/nxp/nxp_mcxnx4x_common.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -660,6 +660,79 @@
#io-channel-cells = <1>;
};

micfil: micfil@10c000 {
#address-cells = <1>;
#size-cells = <0>;

compatible = "nxp,micfil";
reg = <0x10c000 0x1000>;

interrupts = <48 0>;
clocks = <&syscon MCUX_MICFIL_CLK>;
quality-mode = <1>;
cic-decimation-rate = <0>;
fifo-watermark = <15>;
sample-rate = <16000>;

status = "disabled";

channel0: micfil-channel@0 {
reg = <0>;
dc-remover-cutoff-freq = <2>;
decimation-filter-gain = <4>;
status = "disabled";
};

channel1: micfil-channel@1 {
reg = <1>;
dc-remover-cutoff-freq = <2>;
decimation-filter-gain = <4>;
status = "disabled";
};

channel2: micfil-channel@2 {
reg = <2>;
dc-remover-cutoff-freq = <2>;
decimation-filter-gain = <4>;
status = "disabled";
};

channel3: micfil-channel@3 {
reg = <3>;
dc-remover-cutoff-freq = <2>;
decimation-filter-gain = <4>;
status = "disabled";
};

channel4: micfil-channel@4 {
reg = <4>;
dc-remover-cutoff-freq = <2>;
decimation-filter-gain = <4>;
status = "disabled";
};

channel5: micfil-channel@5 {
reg = <5>;
dc-remover-cutoff-freq = <2>;
decimation-filter-gain = <4>;
status = "disabled";
};

channel6: micfil-channel@6 {
reg = <6>;
dc-remover-cutoff-freq = <2>;
decimation-filter-gain = <4>;
status = "disabled";
};

channel7: micfil-channel@7 {
reg = <7>;
dc-remover-cutoff-freq = <2>;
decimation-filter-gain = <4>;
status = "disabled";
};
};

enet: ethernet@40100000 {
compatible = "nxp,enet-qos";
reg = <0x40100000 0x1200>;
Expand Down