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Enable i2s_codec sample on mcxn5xx_evk #96954

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Enable i2s_codec sample on mcxn5xx_evk #96954

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3919bdb
soc: mcxnx4x: Instantiate MICFIL
VitekST Aug 28, 2025
542bfb4
board: mcx_n5xx: Enable MICFIL and da7212 codec on mcx_n5xx
TomasBarakNXP Oct 3, 2025
89451d2
board: mcx_nx4x: format board.c
TomasBarakNXP Oct 3, 2025
2c9d813
samples: i2s_codec: enable i2s_codec sample for mcx_n5xx_evk
TomasBarakNXP Oct 3, 2025
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52 changes: 26 additions & 26 deletions boards/nxp/mcx_nx4x_evk/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -18,14 +18,16 @@
#define BOARD_USB_PHY_TXCAL45DM (0x07U)

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@dbaluta dbaluta Oct 3, 2025 •
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A commit message should be focused on why the changes is needed and less on what is does. What it does should be somehow obvious from the code (if it is not then explain it briefly in the commit message).

So here your commit message should be something like this:

 board: mcx_nx4x: Fix formatting 

In order to make style more consistent and code easier to read
fix some style issues:
- add enum values each on a single line
- fixes multiple whitespaces in macro definitions

Signed-off-by: Tomas Barak <[email protected]>

If those were detected by a tool (e.g checkpatch.pl) please also mention this in the commit message.

Also, this change can be marked as trivial sent in a different PR and merged faster your if current PR is delayed by some dependencies.

usb_phy_config_struct_t usbPhyConfig = {
BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM,
BOARD_USB_PHY_D_CAL,
BOARD_USB_PHY_TXCAL45DP,
BOARD_USB_PHY_TXCAL45DM,
};
#endif

/* Board xtal frequency in Hz */
#define BOARD_XTAL0_CLK_HZ 24000000U
#define BOARD_XTAL0_CLK_HZ 24000000U
/* Core clock frequency: 150MHz */
#define CLOCK_INIT_CORE_CLOCK 150000000U
#define CLOCK_INIT_CORE_CLOCK 150000000U
/* System clock frequency. */
extern uint32_t SystemCoreClock;

Expand All @@ -34,21 +36,21 @@ void power_mode_od(void)
{
/* Set the DCDC VDD regulator to 1.2 V voltage level */
spc_active_mode_dcdc_option_t opt = {
.DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
.DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
};
SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);

/* Set the LDO_CORE VDD regulator to 1.2 V voltage level */
spc_active_mode_core_ldo_option_t ldo_opt = {
.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
};
SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_opt);

/* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */
spc_sram_voltage_config_t cfg = {
.operateVoltage = kSPC_sramOperateAt1P2V,
.operateVoltage = kSPC_sramOperateAt1P2V,
.requestVoltageUpdate = true,
};
SPC_SetSRAMOperateVoltage(SPC0, &cfg);
Expand Down Expand Up @@ -115,14 +117,12 @@ void board_early_init_hook(void)
#endif

/* Set up PLL0 */
const pll_setup_t pll0Setup = {
.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) |
SCG_APLLCTRL_SELP(13U),
.pllndiv = SCG_APLLNDIV_NDIV(8U),
.pllpdiv = SCG_APLLPDIV_PDIV(1U),
.pllmdiv = SCG_APLLMDIV_MDIV(50U),
.pllRate = 150000000U
};
const pll_setup_t pll0Setup = {.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) |
SCG_APLLCTRL_SELP(13U),
.pllndiv = SCG_APLLNDIV_NDIV(8U),
.pllpdiv = SCG_APLLPDIV_PDIV(1U),
.pllmdiv = SCG_APLLMDIV_MDIV(50U),
.pllRate = 150000000U};
/* Configure PLL0 to the desired values */
CLOCK_SetPLL0Freq(&pll0Setup);
/* PLL0 Monitor is disabled */
Expand All @@ -136,15 +136,15 @@ void board_early_init_hook(void)

CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ);

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I wonder if you can enable them in separate patches? If one of them breaks the system one of them would have a hard time doing a bisection.

Please use 1 commit per a logical change so that code can be easier to be reviewed and also bisection and debugging in the future be easier.

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(micfil))
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) || \
DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(micfil))
/* < Set up PLL1 */
const pll_setup_t pll1_Setup = {
.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) |
SCG_SPLLCTRL_SELP(1U),
.pllndiv = SCG_SPLLNDIV_NDIV(25U),
.pllpdiv = SCG_SPLLPDIV_PDIV(10U),
.pllmdiv = SCG_SPLLMDIV_MDIV(256U),
.pllRate = 24576000U};
const pll_setup_t pll1_Setup = {.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) |
SCG_SPLLCTRL_SELP(1U),
.pllndiv = SCG_SPLLNDIV_NDIV(25U),
.pllpdiv = SCG_SPLLPDIV_PDIV(10U),
.pllmdiv = SCG_SPLLMDIV_MDIV(256U),
.pllRate = 24576000U};

/* Configure PLL1 to the desired values */
CLOCK_SetPLL1Freq(&pll1_Setup);
Expand Down Expand Up @@ -356,8 +356,8 @@ void board_early_init_hook(void)
while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK)) {
};
}
SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK |
SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
SYSCON->AHBCLKCTRLSET[2] |=
SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
/* xtal = 20 ~ 30MHz */
SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
Expand All @@ -367,8 +367,8 @@ void board_early_init_hook(void)
break;
}
}
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK |
SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
SYSCON->CLOCK_CTRL |=
SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
CLOCK_EnableClock(kCLOCK_UsbHs);
CLOCK_EnableClock(kCLOCK_UsbHsPhy);
CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ);
Expand Down