[PowerPC] Replace vspltisw+vadduwm instructions with xxleqv+vsubuwm for adding the vector {1, 1, 1, 1}

[Himadhith]

This patch optimizes vector addition operations involving all-ones vectors by leveraging the generation of vectors of -1s(using xxleqv, which is cheaper than generating vectors of 1s(vspltisw). These are the respective vector types.
v2i64: A + vector {1, 1}
v4i32: A + vector {1, 1, 1, 1}
v8i16: A + vector {1, 1, 1, 1, 1, 1, 1, 1}
v16i8: A + vector {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}

The optimized version replaces vspltisw (4 cycles) with xxleqv (2 cycles) using the following identity:
A - (-1) = A + 1.

[llvmbot]

@llvm/pr-subscribers-backend-powerpc

Author: None (Himadhith)

Changes

This patch leverages generation of vector of -1s to be cheaper than vector of 1s to optimize the current implementation for A + vector {1, 1, 1, 1}.

In this optimized version we replace vspltisw (4 cycles) with xxleqv (2 cycles) using the following identity:
A - (-1) = A + 1.

---

Full diff: https://github.com/llvm/llvm-project/pull/160882.diff

1 Files Affected:

• (modified) llvm/lib/Target/PowerPC/PPCInstrVSX.td (+4)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index 4e5165bfcda55..dc850d2470cfd 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -3627,6 +3627,10 @@ def : Pat<(v4i32 (build_vector immSExt5NonZero:$A, immSExt5NonZero:$A,
                                immSExt5NonZero:$A, immSExt5NonZero:$A)),
           (v4i32 (VSPLTISW imm:$A))>;
 
+// Optimise for vector of 1s addition operation
+def : Pat<(add v4i32:$A, (build_vector (i32 1), (i32 1), (i32 1), (i32 1))),
+          (VSUBUWM $A, (v4i32 (COPY_TO_REGCLASS (XXLEQVOnes), VSRC)))>;
+
 // Splat loads.
 def : Pat<(v8i16 (PPCldsplat ForceXForm:$A)),
           (v8i16 (VSPLTHs 3, (MTVSRWZ (LHZX ForceXForm:$A))))>;

[lei137]

I'm guessing this is not ready to be reviewed as it need https://github.com/llvm/llvm-project/pull/160476/files to be in first enable to show the difference.

[Himadhith]

I'm guessing this is not ready to be reviewed as it need https://github.com/llvm/llvm-project/pull/160476/files to be in first enable to show the difference.

Yes as soon as the NFC patch gets merged I will rebase and the file should reflect the changes. Should I keep this as a draft till then?

[tonykuttai]

Does this work only for v4i32 vector types? Why not v2i64, v8i16 and v16i8 types?

[Himadhith]

I tried to add Patterns for the other 3 types which are not present, I noticed that for v2i64 type the tablegen pattern matching was not working as it is generating the following ISAs:

	vspltisw 3, 1
	vupklsw 3, 3
	vaddudm 2, 2, 3

Which is difficult to replace gracefully using tablegen method. Instead, opting for DAG combiner method to handle this case in the backend.

[tonykuttai]

Same as above comment. Support v2i64, v8i16 and v16i8 types as well ?

[Himadhith]

Will add a NFC patch shortly to address the other 3 types.

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[tonykuttai]

Please modify the description to reflect that

• ADD operation substituted with SUB
• Build vector of all 1s in RHS getting replaced with Build vector of all -1s

[tonykuttai]

Please investigate why this got affected.

[Himadhith]

This was because the code did not check for VSX attribute. The hasVSX() check fixed this.

[tonykuttai]

BUILD_VECTOR have to be on the RHS. We don't need the swap here.

[Himadhith]

Done.

[tonykuttai]

Thanks for addressing the comments. LGTM

[Himadhith]

This patch does not handle v1i128 vector type because it does not emit the instruction vspltisw.

# %bb.0:                                # %entry
        addis 3, 2, .LCPI4_0@toc@ha
        addi 3, 3, .LCPI4_0@toc@l
        lxvd2x 0, 0, 3
        xxswapd 35, 0
        vadduqm 2, 2, 3
        blr
        .long   0
        .quad   0