Minor Release v3.1.0

Description

• adding QSFP & PCA9555 I2C support to BittWare
• Upgrading to axi-pcie-core-core@v6.2.0

Full Changelog: v3.0.0...v3.1.0

Major Release v3.0.0

Description

• upgrading to axi-pcie-core@v6.0.0
  • which changes BAR0 from 32b to 64b address

Full Changelog: v2.14.0...v3.0.0

Minor Release v2.14.0

Pull Requests Since v2.13.0

Unlabeled

1. #10 - Adding FEC optional support to PGPv4

Pull Request Details

Adding FEC optional support to PGPv4

Author:	Larry Ruckman ruckman@slac.stanford.edu
Date:	Wed Oct 1 17:15:10 2025 -0700
Pull:	#10 (1350 additions, 63 deletions, 25 files changed)
Branch:	slaclab/PGPv4-FEC

Notes:

Description

• Implementing IEEE802.3-2015 Clause 74 ("Fire Code Error Correction") as an option sublayer between the GT and PGPv4 protocol layers
  • RS(528, 514) code over GF(2^8)
  • Depended on the IEEE 802.3 Clause 74 IP core

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Release generated with SLAC ruckus releaseGen script

Minor Release v2.13.0

What's Changed

• Update README.md by @paulinog in #11
• Update README.md adding a top-level diagram by @paulinog in #12
• updating XilinxVariumC1100 HTSP to use 156.25MHz refClk
• upgrading to surf (v2.63.0)
• C1100: HbmDmaBufferV2 API updates

New Contributors

• @paulinog made their first contribution in #11

Full Changelog: v2.12.0...v2.13.0

Minor Release v2.12.0

Description

• Upgrading to SURF@v2.62.0

Full Changelog: v2.11.0...v2.12.0

Minor Release v2.11.0

Description

• adding dynamic rx/tx polarity configuration support to PGP4

Full Changelog: v2.10.0...v2.11.0

Minor Release v2.10.0

Description

• optimizing XilinxVariumC1100Pgp HBM clock freq (all targets)
• adding XilinxVariumC1100Pgp4_12Gbps
• adding XilinxVariumC1100Pgp4_13Gbps
• adding XilinxVariumC1100Pgp4_17Gbps
• adding XilinxVariumC1100Pgp4_18Gbps
• adding XilinxVariumC1100Pgp4_20Gbps

Full Changelog: v2.9.0...v2.10.0

Minor Release v2.9.0

What's Changed

• HTPS updates by @ruck314 in #6
• Htps update by @ruck314 in #7
• HTPS Updates and Performance Updates required to get C1100's HBM buffer to achieve 100Gb/s per lane by @ruck314 in #8

Full Changelog: v2.8.0...v2.9.0

v1.8.2

Description

• updating for rogue v5.16.0
• updating to updatePcieFpga updates from Bruce

Full Changelog: v1.8.1...v1.8.2

Minor Release v2.8.0

Description

• Adding "auto disable CDR in the QSFP feature" to all the targets with link rate < 25Gb/s/lane

Full Changelog: v2.7.0...v2.8.0